Content locality-based caching in a data storage system

ABSTRACT

A data storage caching architecture supports using native local memory such as host-based RAM, and if available, Solid State Disk (SSD) memory for storing pre-cache delta-compression based delta, reference, and independent data by exploiting content locality, temporal locality, and spatial locality of data accesses to primary (e.g. disk-based) storage. The architecture makes excellent use of the physical properties of the different types of memory available (fast r/w RAM, low cost fast read SSD, etc) by applying algorithms to determine what types of data to store in each type of memory. Algorithms include similarity detection, delta compression, least popularly used cache management, conservative insertion and promotion cache replacement, and the like.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application U.S. Ser.No. 13/366,846 entitled Pre-Cache Similarity-Based Delta Compression foruse in a Data Storage System, filed Feb. 6, 2012, which is herebyincorporated herein by reference in its entirety.

U.S. patent application U.S. Ser. No. 13/366,846 claims the benefit ofthe following provisional applications, each of which is herebyincorporated herein by reference in its entirety: U.S. Ser. No.61/441,976 entitled Intelligently Coupled Array of SSD and HDD, filedFeb. 11, 2011; U.S. Ser. No. 61/447,208 entitled Effective PageClassification and Delta Encoding AND Buffer Cache—Temporal and ContentLocalities, filed Feb. 28, 2011; and U.S. Ser. No. 61/497,549 entitledConservative Insertion and Promotion Cache Replacement Algorithm, filedJun. 16, 2011.

U.S. patent application Ser. No. 13/366,846 is a continuation-in-part ofU.S. patent application Ser. No. 12/762,993 entitled System and Methodfor Data Storage, filed Apr. 19, 2010, which is hereby incorporatedherein by reference in its entirety.

U.S. patent application Ser. No. 12/762,993 claims priority to U.S.provisional patent application Ser. No. 61/174,166 entitled System andMethod for Data Storage, filed Apr. 30, 2009, which is herebyincorporated herein by reference in its entirety.

BACKGROUND

1. Field

The present invention relates to data caching techniques, and moreparticularly to content locality-based caching in a data storage system.

2. Description of the Related Art

While data storage capacity and central processing unit (CPU) processingpower have experienced rapid growth in the past, improvement in databandwidth and access times of disk input/output (I/O) systems have notkept pace. As a result, there is an ever-widening speed gap between CPUand disk I/O systems. Disk arrays can improve overall I/O throughput,but random access latency is still very high because of mechanicaloperations involved. Large buffers and deep cache hierarchy can improvelatency but the resulting access time reduction is very limited.

SUMMARY

Recent developments of flash memory-based solid-state drives (SSDs) havebeen very promising, with rapid increases in capacity and decreases incost. Because SSDs are based on semi-conductor technology, they mayprovide great advantages including enabling high-speed random reads, lowpower consumption, compact size, shock resistance, and the like.However, limitations that result from the physical properties of SSDsinclude write and erase times that are very slow compared to read times,and a significantly limited number of write/erase cycles before failureof a block.

The above physical properties and operational characteristics of SSDspresent unique challenges in designing a SSD-based mass storagehierarchy. Therefore, we disclose herein cache management methods andsystems that can address these unique challenges by effectively managingan SSD-based storage hierarchy to provide higher I/O performance, lowercost, longer durability, and higher data reliability.

Also, while the capacity of disk drives grows rapidly, theirelectromechanical parts have held down the improvement of theirperformance. Caching plays a critical role in modern systems, the cachebridging the gap between a disk drive and the main memory. Applyingcontent locality techniques to cache design may provide a significantimprovement in performance, particularly when combined with thetechniques for SSD use and optimization described herein. Contentlocality refers to the characteristic that many data blocks in a datastorage system may share similar or even the same content.

The recent advancement of machine virtualization has made contentlocality even stronger. In a virtual machine environment, each guestvirtual machine is allocated a virtual disk image for storing a guestoperating system, application code, and data. In a virtualized systemwith several guest machines, each allocated virtual disk image may storethe same operating system and at least a portion of the application codemay be the same. As a result, a significantly high percentage of datablocks in a data storage system that supports virtual disk images sharesimilar or the same content. For better resource utilization, lowerpower consumption, easy management, and strong process isolation, datacenter servers may serve hundreds of virtual machines to provide serviceto thousands of computers and mobile devices. This may result in muchmore data redundancy than would be present when running a single OS on adata center server. Therefore cache management techniques, methods, andsystems described herein may find significant benefit in data centervirtualization (e.g. cloud computing/storage).

Because large files and collections of files may show strong contentlocality due to large amounts of data redundancy, the cache techniques,methods, and systems described herein may help eliminate storingredundant data through the efficient use of compression algorithms anddelta encoding. Delta encoding exploits the concept that many datablocks can be represented as small patches/deltas with respect to one ormore reference pages.

Other methods and systems described herein may exploit content localityin optimizing SSD storage design. Pages stored on SSD may be classifiedinto three different categories—delta, reference, and independentpages—to make best use of high read performance of the SSD and tominimize write operations. Such page classification and storage may bereferred to herein as “DRIPStore”.

An SSD-based storage hierarchy may also take advantage of highperformance, low cost multi-core graphics processing units (GPU) andCPUs that may be capable of supercomputing performance at very low cost.Current technology GPUs may draw very little power while deliveringperformance levels of hundreds of GFLOPS which may make it possible todo on-the-fly computation for disk I/O operations. Next-generationmobile GPUs are expected to nearly double this performance with asimilar power envelope.

Various embodiments described herein present a new data storagearchitecture for higher performance, extended operating life forsolid-state memory elements, lower power consumption, improvedreliability, and reduced cost. The new architecture may also exploitemerging semi-conductor technologies. Embodiments described herein mayinclude SSD storage, RAM, and optionally primary storage and anintelligent processing unit. Generally, the SSD may store seldom changedand mostly read data (e.g. reference blocks) and the RAM may storedeltas (or patches) of data blocks of active I/Os with respect toreference data blocks stored in the SSD. The RAM may also store mostrecently/frequently accessed independent blocks (blocks that are notrepresented by a delta/reference block combination). In such anembodiment, a host processor may perform the techniques and methodsdescribed herein, including without limitation similarity detection,delta derivations upon I/O writes, combination of deltas with referenceblocks in response to I/O reads, quantifying content popularities ofblocks, managing cache by exploiting temporal/spatial/contentlocalities, and other necessary functions for interfacing the storage tothe host. In embodiments that include primary storage, the SSD and theprimary storage may also be coupled by a high speed GPU/CPU/MCU thatperforms the techniques and methods described herein, including withoutlimitation similarity detection, delta derivations upon I/O writes,combination of deltas with reference blocks in response to I/O reads,quantifying content popularities of blocks, managing cache by exploitingtemporal/spatial/content localities, and other necessary functions forinterfacing the storage to the host. For this embodiment, the SSD maystore seldom changed and mostly read data (e.g. reference blocks) andthe primary storage and/or the RAM may store delta blocks that are madeup of many deltas as described above. The HDD and/or RAM may also storemost recently/frequently accessed independent block. Embodiments of theinvention may take advantage of various technologies including: 1) fastread performance of SSD, 2) host accessible RAM, 3) supercomputing speedof GPU/CPU, and 4) reliable/durable/sequential write performance of HDD.By applying the methods and systems described herein that includeoptional primary storage (e.g. HDD), an HDD data block can contain alarge number of small deltas with respect to reference blocks. As aresult, one HDD block read operation accesses enough data to satisfymultiple conventional primary storage I/O operations, thereby improvingdisk I/O performance greatly by replacing the slow access times of HDDswith high speed computation of suitable GPU/CPUs. In addition, randomwrites to SSD may be reduced, increasing life time for SSD. In otherembodiments that may not include primary storage and/or the abovementioned GPU/CPU, the need for HDD block accesses may also be reducedby generating data the HDD block data through combining deltas stored inRAM and reference blocks stored in RAM or SSD.

By further exploiting content locality, temporal locality, and spatiallocality of data, a new data storage architecture manages atwo-component cache consisting of RAM and SSD. The new data storagearchitecture may cache reference blocks (e.g. read-mostly data blockswith popular content), deltas, compact delta blocks that may containlarge numbers of deltas, and independent blocks that show strongtemporal and/or spatial locality. Writes to SSD are reduced by dataplacement algorithms that ensure that data written into SSD may becharacterized as popular, read-mostly, compressed, and generally hot.

The methods and systems described herein may also provide significantimprovements in compression and/or de-duplication of data for cachemanagement and may include: line speed, software-based low CPU-overhead,block level, pre-cache similarity-based delta compression—for use in adata storage system—that is based on using multiple signatures todetermine block similarity. Additional compression and/or de-duplicationtechniques, methods, and systems for use in a data storage system aredescribed herein. These may include line speed, software-based, lowCPU-overhead, block level, pre-cache similarity-based delta compressionthat uses heatmap analysis of signatures for determining referenceblocks.

Additionally, methods, techniques and systems described herein mayleverage data placement in a data storage/cache architecture thatincludes multiple types of memory, including: storing most popularblocks of data as reference blocks in RAM or in an SSD and representingsimilar, associated blocks as a delta from a reference block and storingthat delta in another type of memory.

This disclosure may also include methods for delta compression thatenable bandwidth and/or storage savings including: calculatingsub-signatures of each data block to determine if multiple blocks sharesub-signatures, and storing the most popular block as a reference blockand storing the delta for other associated blocks.

Other methods and systems described herein may combine caching withcontent locality techniques that may include caching selected data basedon content locality. A variant of such methods and systems may includecaching selected data based on content locality and at least one oftemporal and spatial locality. Caching decisions may be made bydynamically determining content popularity of data blocks in addition torecency and frequency of their accesses.

Other methods and systems described herein may include use ofapplication-dependent content locality to deliver improvements in datastorage system performance. Application dependent methods and systemsmay facilitate determining when to move a data block from RAM to anothertype of memory based on application data characteristics in a systemthat is enabled to determine data placement based on content locality.Additionally, this may include automatic tuning of a data storage system(e.g. cache management, SSD and HDD utilization, etc.) that may takeinto consideration content locality and application-specificcharacteristics.

Yet other methods and systems described herein may address contentlocality with pre-fetching in a storage system with data placement basedon content locality, including pre-fetching reference blocks based onknown application needs.

Another method and system described herein may address productconfiguration, such as an environment having a host server running anapplication with RAM on it with attached storage and an SSD, byproviding a device driver that performs pre-cache compression and placesdata based on content locality.

Herein also may be disclosed methods and systems for variants of theabove including without limitation, disk-only configurations, SSD-onlyconfigurations, and hybrid systems that may include only SSD and RAM. Adisk-only configuration may include a disk storage system with blocklevel, line speed, pre-cache data compression and caching based oncontent locality. An SSD-only configuration may include an SSD storagesystem with block level, line speed, pre-cache data compression andcaching based on content locality. Also, a hybrid system may include ahybrid storage system that includes attaching SSD to expand RAM andusing SSD to hold reference blocks, with block level, line speed,pre-cache data compression and caching based on content locality.

In an embodiment of the present invention, the method of contentlocality-based caching includes processing data pertaining to a datastorage system with a processor to determine the content locality of thedata and cache a portion of the processed data. The data associated withthe data storage system may be a pre-cache data. Caching may includecaching a first portion of the processed data in an SSD. The cachedfirst portion of the processed data in the SSD may comprise referenceblocks, delta blocks, and independent blocks. Further, caching mayinclude caching a first portion of the processed data in a RAM. Thefirst portion of the processed data cached in the RAM comprises deltablocks and independent blocks. Further, caching may include caching afirst portion of the processed data in an HDD. The first portion of theprocessed data cached in the HDD comprises delta blocks and independentblocks.

In an embodiment of the present invention, a method may includeprocessing a data block in a data storage system with a processor toproduce signatures, determining similarity of the data block to at leastone reference data block using at least a portion of the signatures, andgenerating cache data representing differences between the data blockand at least one reference data block. Producing the signatures mayinclude generating a hash value for every two or more consecutive bytesof the data block. Determining similarity may include comparingsignature occurrence data for the data block to signature occurrencedata for the reference block. Determining similarity may also includegenerating a wavelet transform for each data block, comparingsub-signatures and wavelet transform coefficients of the wavelettransform for at least one data block and at least one reference block,and producing a histogram of a portion of the signatures. The referenceblock may comprise a block of data for which calculated signaturepopularity exceeds a threshold, which may be a reference blockpopularity threshold. Generating the cache data may include generating adelta block that may include differences between data blocks, at leastone reference block, and meta data to map each data block to at leastone reference block. The delta blocks define the differences betweendata blocks, at least one reference block, and meta data to map eachdata block to at least one reference block.

In an embodiment of the present invention, a method may includeprocessing data blocks with a processor to produce signatures thatfacilitate determining similarity of the data blocks in a data storagesystem, calculating (with the processor) a signature heat map of aportion of the signatures to facilitate determining a reference blockfor similarity-based delta compression of pre-cache data, and generating(with the processor) cache data representing differences between aportion of the data blocks and the determined reference block.Generating the cache data may be based on similarity-based deltacompression of data before it may be stored. Producing the signaturesmay include generating a hash value for every two or more consecutivebytes of a data block. The reference block may comprise a block of datafor which calculated signature popularity exceeds a threshold, which maybe a reference block popularity threshold. Generating cache data mayinclude generating a delta block that includes differences between thedata blocks, at least one reference block, and meta data to map eachdata block to at least one reference block. The signature heat map maybe a two-dimensional array of signature-related data, wherein a firstdimension is the number of possible signature values and a seconddimension is a number of sub-signatures or a number of activeinput/output (I/O) accesses associated with each possible signaturevalue during a period of time. The method may further comprise storingthe reference block in an SSD, a RAM or an HDD portion of a cache memoryof the data storage system. The method may further comprise storing inan SSD or a RAM or an HDD portion of a cache memory of the data storagesystem a delta block comprising cache data that represents differencebetween pre-cache data blocks and the determined reference block.

In an embodiment of the present invention, a method of storing data in acache memory of a data storage system capable of similarity-based deltacompression may comprise receiving at least one of a reference block, apacked delta block, an independent block, and a frequently accessedblock; and storing at least one of the received reference block, thepacked delta block, the independent block, and the frequently accessedblock in an SSD portion of the cache memory. The reference block maycomprise data, a portion of which is common to data blocks. The packeddelta block may comprise a data representing differences between datablocks and at least one reference block. The method may further comprisestoring at least one of the received reference block, the packed deltablock, the independent block, and the frequently accessed block in a RAMportion of the cache memory.

In an embodiment of the present invention, a method of data placement ina cache data storage system may comprise receiving reference blocks ofdata, storing the reference blocks in a first portion of the cache datastorage system, receiving data that represents a delta of a data blockfrom at least one of the stored reference blocks, and storing as a deltablock the data that represents the delta of the data block in a secondportion of the cache data storage system that does not comprise SSDmemory. The reference block may comprise a block of data for whichcalculated signature popularity exceeds a threshold, which may be areference block popularity threshold. The first portion of the cachedata storage system may comprise an SSD or a RAM memory. The secondportion of the cache data storage system may comprise a RAM memory or adisk memory. The delta block may include data that represents deltas ofdata blocks. The reference blocks may facilitate similarity-based deltacompression. Storing the reference blocks comprises storing the mostpopular reference blocks, which may include blocks containing signaturesthat exceed at least one of a frequency of occurrence threshold andrecency of access threshold among data blocks.

In an embodiment of the present invention, a method of contentlocality-based caching may comprise receiving data that is associatedwith a data storage system with a processor, processing the data withthe processor to determine its content locality, processing the datawith the processor to determine its temporal locality, and caching aportion of the processed data based on its determined content andtemporal locality. The data that may be associated with the data storagesystem is the pre-cache data. Caching may include caching the firstportion of the processed data in an SSD memory. The first portion of theprocessed data may comprise reference blocks, delta blocks, orindependent blocks. Caching may also include caching the first portionof the processed data in a RAM or an HDD memory. The first portion ofthe processed data may comprise delta blocks, or independent blocks.

In an embodiment of the present invention, a method of contentlocality-based caching may comprise receiving data that is associatedwith a data storage system with a processor, processing the data withthe processor to determine its content locality, processing the datawith the processor to determine its spatial locality, and caching aportion of the processed data based on its determined content andspatial locality. The data that may be associated with the data storagesystem is pre-cache data. Caching may comprise caching a first portionof the processed data in an SSD memory. The first portion of theprocessed data may comprise reference blocks, delta blocks, orindependent blocks. The caching may comprise caching a first portion ofthe processed data in a RAM or in a HDD memory. The first portion of theprocessed data may comprise delta blocks or independent blocks.

In an embodiment of the present invention, a method of contentlocality-based caching may comprise receiving data pertaining to a datastorage system with a processor, processing the data with the processorto determine its content locality, spatial locality, and temporallocality, and caching a portion of the processed data based on itsdetermined content, spatial, and temporal locality. The data pertainingto data storage system may be pre-cache data. The caching may comprisecaching the first portion of the processed data in an SSD memory. Thefirst portion of the processed data may comprise reference blocks, deltablocks, or independent blocks. The caching may comprise caching a firstportion of the processed data in a RAM or an HDD memory. The firstportion of the processed data may comprise delta blocks or independentblocks.

In an embodiment of the present invention, a method may compriseprocessing data blocks with a processor to produce popularitysub-signatures that facilitate determining similarity of the datablocks, comparing the popularity sub-signatures to determine a mostpopular data block, storing the most popular data block as a referenceblock, and storing deltas for other data blocks that representdifferences from the reference block. The producing popularitysub-signatures may comprise generating sub-signatures for data blocks ina data storage system. Comparing the popularity sub-signatures mayinclude identifying a subset for each data block comprising at least onesub-signature that occurs more frequently than other sub-signatures ofthe sub-signatures for each of the data blocks, determining thesub-signatures that occur most frequently across the data blocks, anddetermining the popularity across the data blocks of each sub-signaturein each subset. The subset for each data block may include more than onesub-signature.

In an embodiment of the present invention, a method of losslesscompression-based caching may comprise receiving data pertaining to adata storage system with a processor, and compressing the data with theprocessor by applying a similarity-based delta compression algorithm tofacilitate making more of the received data available to the processorin a cache of the data storage system than would be made availablewithout compression.

In an embodiment of the present invention, a method of locality-basedcaching of application-dependent content may comprise receiving cacheddata associated with an application executing on a processor, processingthe data with the processor to determine its content locality, analyzingthe data with the processor to identify application-specificcharacteristics of the data, and identifying a cached portion of thedata to be moved from a RAM portion of a cache to another type of memorybased on the determined content-locality and identifiedapplication-specific characteristics.

In an embodiment of the present invention, a method may compriseaccessing a data storage system with a processor to determine dataplacement based on content locality, and pre-fetch reference blocksassociated with an application being executed by the processor based onan assessment of data needs of the application.

In an embodiment of the present invention, a method of facilitatingpre-cache data compression may comprise deploying a device driver thatperforms pre-cache compression and data placement based on contentlocality, wherein the data can be placed in at least one of a RAM, anSSD, and a mass storage.

In an embodiment of the present invention, a method of contentlocality-based data storage may comprise taking a data block in a datastorage system including a cache storage and a mass storage, processingthe data block with a processor to determine its content locality,generating compressed cache data representing the data block, andcaching a portion of the processed data based on its determined contentlocality. The cache storage may be a RAM and the mass storage may be adisk or an SSD. Further, at least one of the cache storage and the massstorage may comprise an SSD and the mass storage may further comprise adisk.

In an embodiment of the present invention, a method may comprise takinga data block in a hybrid data storage system including a cache storageand a mass storage, wherein the cache storage comprises a RAM and anSSD; processing the data block with a processor to determine its contentlocality, storing in the SSD reference blocks selected to facilitatesimilarity-based pre-cache delta compression; generating compressed datarepresenting the data block based on the differences between the datablock and at least one of the reference blocks; and caching thecompressed data based on the determined content locality.

In an embodiment of the present invention, a method may compriseaccessing a block of data, accessing an SSD memory to retrieve areference block based on similarity of the block of data to thereference block, determining differences between the block of data andthe reference block, and recording the determined differences in a cachepage configured to cache the determined differences for data blocks.

In an embodiment of the present invention, a method may comprisereceiving a request for a block of data, accessing a cached delta pagethat identifies differences between the block of data and a similarreference block, accessing the similar reference block from an SSDmemory, and generating the requested block of data by applying thedifferences accessed in the delta page to the reference block. Thecached delta page may be accessible in a RAM.

In an embodiment of the present invention, a method of generating areference block for storing in a cache may comprise generatingsub-signatures for data blocks in a data storage system, identifying asubset for each data block comprising the most frequently occurringsub-signatures of the sub-signatures for each of the data blocks,determining the sub-signatures that occur most frequently across thedata blocks, determining the popularity across the data blocks of eachsub-signature in each subset, and selecting a data block with thegreatest determined popularity to be stored as a reference block. Themethod may further comprise recording differences between the selecteddata block and a portion of the data blocks in a delta page. The subsetfor each data block may include more than one of the most frequentlyoccurring sub-signatures.

In an embodiment of the present invention, a method of cache data blockmanagement may comprise providing a list comprising sub-lists forstoring data associated with data blocks, receiving an indication ofaccess of a data block in a data storage system, determining if dataassociated with the data block appears in any of the sub-lists, andbased on the determination, performing one of adding the data associatedwith the data block to a first sub-list, and promoting the dataassociated with the data block to a higher position in the list. Thefirst sub-list may be a data block cache candidate sub-list. Promotingthe data associated with the data block to a higher position in the listmay comprise making the data associated with the data block accessiblethrough a different sub-list if the indication of access is a subsequentindication of access of the data block. The subsequent indication ofaccess may be tunable and may be determined based on I/O access size ordata block size. Promoting the data associated with the data block tothe higher position in the list may comprise making the data associatedwith the data block available at higher position within a sub-list. Thedata associated with a data block in a lowest position of a sub-list maybe removed from the sub-list when the data associated with the datablock is added to the sub-list. Adding the data associated with the datablock to the first sub-list results in data associated with the datablock in the lowest position of the first sub-list to be removed fromthe list. The data associated with the data block may be removed from asub-list if a subsequent indication of access to the data block is notreceived within a predetermined number of cache misses. Thepredetermined number of cache misses may be based in part on a maximumnumber of positions in the sub-list. If the sub-list from which the dataassociated with a data block is removed is a RAM sub-list or an SSDsub-list, the removed data may be made accessible in another sub-list.The list may comprise a RAM sub-list, an SSD sub-list, and a candidatesub-list. The data associated with the data block in the candidatesub-list that may be promoted is made accessible in the SSD sub-list.The data associated with the data block in the SSD sub-list that may bepromoted is made accessible in the RAM sub-list. The data associatedwith the data block stored in the list may comprise pointers to cacheddata blocks. The data associated with the data block stored in the listmay comprise linked-list pointers to cached data blocks or meta data.The data associated with the data block that is made accessible throughthe list comprises a linked-list pointer, wherein the list may be alinked list. At least one of the sub-lists may be a linked list. Thedata associated with the data block may be made accessible in the firstsub-list if it is not yet available in any sub-list. The sub-lists maybe non-overlapping and a portion of the sub-lists may be overlapping.

These and other systems, methods, objects, features, and advantages ofthe present invention may be apparent to those skilled in the art fromthe following detailed description of the preferred embodiment and thedrawings. All documents mentioned herein are hereby incorporated intheir entirety by reference.

BRIEF DESCRIPTION OF THE FIGURES

The invention and the following detailed description of certainembodiments thereof may be understood by reference to the followingfigures:

FIG. 1 depicts a block diagram of a data storage system using an SSDmemory.

FIG. 2 depicts a block diagram of a hybrid data storage system using anSSD as a cache and an HDD for mass data storage.

FIG. 3 depicts a block diagram of a hybrid data storage system using aGPU to control reads, writes, and erases to an SSD and an HDD.

FIG. 4 depicts a block diagram of a write operation by the data storagesystem of FIG. 3.

FIG. 5 depicts a high-level logic flowchart showing a write operation bythe data storage system of FIG. 3.

FIG. 6 depicts a block diagram of a read operation by the data storagesystem of FIG. 3.

FIG. 7 depicts a high-level logic flowchart showing a read operation bythe data storage system of FIG. 3.

FIG. 8 depicts a block diagram of the data storage system of FIG. 3implemented at the disk controller level.

FIG. 9 depicts a block diagram of the data storage system of FIG. 3implemented at the host bus adaptor level.

FIG. 10 depicts a block diagram of the data storage system of FIG. 3implemented at the host bus adaptor level with external SSD.

FIG. 11 depicts a block diagram of the data storage system of FIG. 3implemented by software.

FIG. 12 depicts a block diagram of a hybrid data storage system usingsoftware on a host computer to control reads, writes, and erases to anSSD and an HDD.

FIG. 13 depicts a block diagram of a software-based data storage systemcache management system using the methods and systems described herein.

FIG. 14 depicts a block diagram of a write operation by the data storagesystem of FIG. 13.

FIG. 15 depicts a high-level logic flowchart showing a write operationby the data storage system of FIG. 13.

FIG. 16 depicts a block diagram of a read operation by the data storagesystem of FIG. 13.

FIG. 17 depicts a high-level logic flowchart showing a read operation bythe data storage system of FIG. 13.

FIG. 18 depicts a high-level logic flowchart showing a process ofdetermining reference blocks from cached independent blocks.

FIG. 18 depicts a high-level logic flowchart showing a process of deltacompression on a cache miss.

FIG. 20 depicts a bar graph showing I/O speedup factors achieved by thedata storage system of FIG. 12 in comparison with a baseline systemusing an SSD as an LRU disk cache on top of an HDD, with both systemsrunning identical sets of standard benchmarks and using a 4 KB blocksize.

FIG. 21 depicts a bar graph showing I/O speedup factors achieved by thedata storage system of FIG. 12 in comparison with a baseline systemusing an SSD as an LRU disk cache on top of an HDD, with both systemsrunning identical sets of standard benchmarks and using an 8 KB blocksize.

FIG. 22 depicts a bar graph showing HDD disk I/O reductions achieved bythe data storage system of FIG. 12 in comparison with a baseline systemusing an SSD as an LRU disk cache on top of an HDD, with both systemsrunning identical sets of standard benchmarks and using a 4 KB blocksize.

FIG. 23 depicts a bar graph showing HDD disk I/O reductions achieved bythe data storage system of FIG. 12 in comparison with a baseline systemusing an SSD as an LRU disk cache on top of an HDD, with both systemsrunning identical sets of standard benchmarks and using an 8 KB blocksize.

FIG. 24 depicts a bar graph showing estimated percentages of independentblocks stored by the system of FIG. 12 running a set of standardbenchmarks and using a 4 KB block size.

FIG. 25 depicts a bar graph showing average sizes of deltas stored bythe system of FIG. 12 running a set of standard benchmarks and using a 4KB block size.

FIG. 26 depicts a bar graph showing a comparison of average RAM cacheI/O rates of delta caching by the system of FIG. 12 and data blockcaching in a DRAM buffer.

FIG. 27 depicts a bar graph showing run time write I/O reductions to anSSD.

FIG. 28 depicts sub-block signatures and heatmap concepts.

FIG. 29 depicts and exemplary data layout based on a selected referenceblock.

FIG. 30 depicts a read process and a write process for exploitingcontent locality to optimize SSD storage design.

FIG. 31 depicts a reference page selection process.

FIG. 32 depicts a block diagram of a conservative insertion andpromotion list.

FIG. 33 depicts a block diagram of an embodiment including RAM layoutand RAM cache.

FIG. 34 depicts a method of compression/de-duplication in a cachesubsystem of a data storage system.

FIG. 35 depicts an alternate method of compression/de-duplication in acache subsystem of a data storage system.

FIG. 36 depicts a method of storing data in a cache memory of a datastorage system that is capable of similarity-based delta compression.

FIG. 37 depicts a method of differentiated data storage in a cachememory system.

FIG. 38 depicts a method of caching data based on at least one of datacontent locality and data temporal locality.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S)

In the summary above and in the detailed description, and the claimsbelow, and in the accompanying drawings, reference is made to particularfeatures (including method steps) of the invention. It is to beunderstood that the disclosure of the invention in this specificationincludes all possible combinations of such particular features. Forexample, where a particular feature is disclosed in the context of aparticular aspect or embodiment, or a particular claim, that feature canalso be used, to the extent possible, in combination with and/or in thecontext of other particular aspects and embodiments of the invention,and in the invention generally.

Where reference is made herein to a method comprising two or moredefined steps, the defined steps can be carried out in any order orsimultaneously (except where the context would indicate otherwise), andthe method can include one or more other steps which are carried outbefore any of the defined steps, between two of the defined steps, orafter all the defined steps (except where the context would indicateotherwise).

A host computer system shall be understood to mean any computer systemthat uses and accesses a data storage system for data read and datawrite operations. Such host system may run applications such asdatabases, file systems, web services, and so forth.

SSD shall be understood as any solid state disks such as NAND gate flashmemory, NOR gate flash memory, or any nonvolatile solid state memorieshaving the properties of fast reads, slow writes, and limited life timedue to wearing caused by write operations.

Mass storage may be understood to include hard disk drives (HDDs)including but not limited to hard disk drives, nonvolatile RAM (NVRAM),MEMS storage, and battery backed DRAM. Although the descriptions in thisinvention concentrate on hard disk drives with spinning disks, generallyany type of non-volatile storage can be used in place of hard diskdrive.

Intelligent processing unit shall be understood to mean any computationengine capable of high performance computation and data processing,including but not limited to GPU (for graphic processing unit), CPU (forcentral processing unit), embedded processing unit, and MCU (for microcontroller unit). The term intelligent processing unit and GPU/CPU areused interchangeably in this document.

The term “HBA” shall mean any host bus adaptor that connects a storagedevice to a host through a bus, such as PCI, PCI-Express, PCI-X,InfiniBand, HyperTransport, and alike. Examples of HBAs include SCSIPCI-E card, SATA PCI-E card, iSCSI adaptor card, Fibre Channel PCI-Ecard, etc.

The term “LBA” shall mean a logic block address that represents thelogical location of a data block in a storage system. A host computermay use this address to read or write a data block.

FIG. 1 depicts a block diagram of a known data storage system consistingof a host computer 100 that reads data from and writes data to aNAND-gate flash, NOR-gate flash, or other known SSD memory chip 102. Asdescribed above, this simple system provides I/O performance limited tothat available from SSD technology and limited memory chip operatinglife based on SSD limitations described herein and elsewhere.

FIG. 2 depicts a block diagram of a similar known data storage systemconsisting of a host computer 100, an SSD 104 used as a lower levelstorage cache, and an HDD 200 for primary data storage. The performanceincrease from using the SSD 104 can be limited in part because storageI/O requests do not take advantage of data locality. In addition, largequantities of random writes may slow down the SSD performance andshorten the operating life of an SSD.

As shown in FIG. 3, certain preferred embodiments of the invention mayprovide significant performance improvements over the systems of FIGS. 1and 2 by intelligently coupling an SSD 304 and primary storage 308 witha high performance GPU/CPU 310 into a high performance primary storagecache based storage system 300. A host computer 302 runs applicationsand accesses data in primary storage via the high performance primarystorage cache 300. The SSD 304 may be any type of Nonvolatile memorysuch as NAND-gate FLASH, NOR-gate FLASH, Phase Change Memory, and thelike. Alternatively it may be any type of SSD or equivalent storage,such as that which is described herein or generally known. The SSD 304may store read data called reference blocks that may be writteninfrequently during primary storage I/O operations. The SSD may storedelta blocks that contain compressed deltas, each of which may bederived at run time to represent the difference between a data block ofan active disk I/O operation and its corresponding reference block. TheSSD may also store the most recently/frequently accessed independentblocks. Other data types may be stored in SSD as well.

The primary storage includes but is not limited to spinning hard diskdrives, NVRAM, battery backed DRAM, MEMS storage, SAN, NAS, virtualstorage, and the like. The primary storage 308 may be used to storedeltas in delta blocks, which are data blocks that contain multipledeltas. A delta, which may be stored in a delta block, may be derived atrun time. The delta may represent the difference between a data block ofan active primary storage I/O operation and its corresponding referenceblock that may be stored in the SSD 304. The intelligent processing unit310 may be any type of computing engine such as a GPU, CPU, or MCU thatmay be capable of doing computations such as similarity detection, deltaderivations upon I/O writes, combining delta with reference blocks uponI/O reads, data compression and decompressions, and other necessaryfunctions for interfacing the storage to the host 302. Although theembodiment of FIG. 3 shows only one SSD 304 and one primary storagemodule 308, it is to be understood that any embodiment may utilize morethan one SSD 304 and more than one primary storage module 308.

Referring now to FIG. 4 which depicts a block diagram of a writeoperation by the data storage system of FIG. 3, in response to an I/Owrite by the host computer 302, the intelligent processing unit 310identifies a reference block 402 in the SSD 304 and computes a delta 404with respect to the identified reference block 402. The write operationmay include the host computer 302 issuing a write request to write adata block 408 in storage. The intelligent processing unit 310 processesthe request and communicates with the SSD 304 and primary storage 308 toserve the write operation. The intelligent processing unit 310 firstidentifies the reference block 402 stored in the SSD 304 thatcorresponds to the data block 408 and derives the delta 404 (difference)by comparing the reference block 402 with the data block 408 to bewritten. The derived delta 404 may be grouped with other previouslyderived deltas and stored in the primary storage 308 as a delta block.Note that the derived delta 404 may be stored in RAM, SSD, and any othermemory suitable for use in a cache memory storage system.

Referring now to FIG. 5, which depicts a high-level logic flowchartshowing a write operation by the data storage system of FIG. 3, a writeoperation may be started by the host computer in step 502. In step 504the intelligent processing unit searches for a corresponding referenceblock in the SSD and computes a delta with respect to the new data blockto be written. In step 508 the intelligent processing unit determineswhether the derived delta is smaller than a predetermined andconfigurable threshold value. If the derived delta is smaller than thethreshold value (Yes), the newly derived delta may be stored in aGPU/CPU delta buffer and the meta data mapping the delta and thereference block may be updated in step 510. The intelligent processingunit groups the new delta with previously derived deltas based on acontent and/or temporal locality property in to a delta block. Whenenough deltas are derived to fill a primary storage data block, thegenerated delta block may be stored in the primary storage in step 514.If step 508 finds that the newly derived delta is larger than thethreshold (No), the original data block may be identified as anindependent block. In step 512 meta data may be updated and theindependent block may be stored unchanged in the SSD if space permits orin the primary storage if space is not available in the SSD.

Referring now to FIG. 6, the host computer 302 issues a read request toread a data block 608 from storage. In response to this read therequested data block 608 is returned by combining a delta 604 with itscorresponding reference block 602 in the intelligent processing unit310. The intelligent processing unit 310 processes the request andcommunicates with the SSD 304 and primary storage 308 (if needed) toservice the read operation.

The intelligent processing unit 310 first determines whether therequested data block 608 has a corresponding reference block 602 storedin the SSD 304. If a corresponding reference block 602 is stored in theSSD 304, the intelligent processing unit 310 accesses the correspondingreference block 602 stored in the SSD 304 and reads the correspondingdelta 608 from either the RAM cache or the primary storage based on therequested data block meta data that is accessible to the intelligentprocessing unit 310. The intelligent processing unit 310 then combinesthe reference block 602 with the delta 604 to obtain the requested datablock 608. The combined data block 608 is then returned to the hostcomputer system 302.

Referring now to FIG. 7, which shows a high-level logic flowchart forread operations, a read operation may be started by the host computer instep 702. At step 704, the intelligent processing unit (GPU/CPU)determines whether or not the requested data block has a referenceblock. If the data block has a reference block (yes), the intelligentprocessing unit searches for the corresponding reference block and thecorresponding delta block in the cache. If no corresponding delta ispresent in the RAM cache of the intelligent processing unit, theintelligent processing unit searches for the corresponding delta in theprimary storage. Once both the reference block and the delta are found,the intelligent processing unit combines the reference block and thedelta to form the requested data block in Step 708. If at step 704 theintelligent processing unit finds that the newly requested data blockdoes not have a corresponding reference block (“No” after Step 704), theintelligent processing unit identifies an independent block in the SSD,the CPU/GPU cache, or the primary storage at step 710 and returns theindependent data block to the host computer at step 712.

Since deltas may generally be small due to data regularity and contentlocality, certain preferred embodiments of the invention store deltas ina compact form so that one SSD or HDD operation contains enough deltasto generate tens or even hundreds of I/Os. The goal may be to convertthe majority of I/Os from the traditional seek-rotation-transfer I/Ooperations on HDD to I/O operations involving mainly SSD reads andhigh-speed computations. The former takes tens of milliseconds whereasthe latter may take tens of microseconds. As a result, the SSD incertain preferred embodiments of the invention may function as anintegral part of a cache memory architecture that takes full advantageof fast SSD read performance while avoiding the drawbacks of SSDerase/write performance. Because of 1) high speed read performance ofreference blocks stored in SSDs, 2) potentially large number of smalldeltas packed in one delta block stored in HDD, and 3) high performanceGPU/CPU coupling the two, certain preferred embodiments of the inventionimprove disk I/O performance greatly.

A first embodiment of the inventive methods and systems described hereinmay be embedded inside a disk controller. Such an embodiment may includea disk controller board that is adapted to include NAND-gate flash SSDor similar device, a GPU/CPU, and a DRAM buffer in addition to theexisting disk control hardware and interfaces such as the host busadapter (HBA). FIG. 8 depicts a block diagram of an HDDcontroller-embedded embodiment. A host system 802 may be connected to adisk controller 820 using a standard interface 812. Such an interfacecan be SCSI, SATA, SAS, PATA, iSCSI, FC, or the like. The flash memory804 may be an SSD, such as to store reference blocks, compact deltablocks, hot independent blocks, and similar data. The intelligentprocessing unit 810 performs logical operations such as deltaderivation, similarity detection, combining delta with reference blocks,managing reference blocks, managing meta data, and other operationsdescribed herein or known for maximizing SSD-based caching. The RAMcache 808 may temporarily store reference blocks, deltas, andindependent blocks for active I/O operations. The HDD controller 820 maybe connected to the HDD 818 by known means through the interface 814.

A second embodiment may implement the methods and systems describedherein at the host bus adaptor (HBA) level by adding the flash SSD,intelligent processing unit, and the DRAM buffer to an existing HBA,such as SCSI, IDE, SATA card, or the like. The new HBA may have aNAND-gate flash SSD or other SSD, an intelligent processing unit (e.g.GPU/CPU), and a small DRAM buffer added to the existing HBA controllogic and interfaces. FIG. 9 depicts a block diagram for implementationof this second embodiment inside the HBA 922. A host system 902 may beconnected to a system bus 918 such as PCI, PCI-Express, PCI-X,HyperTransport, InfiniBand, and the like. The bus interface 912 allowsthe HBA card to be connected to the system bus. The flash memory 904 maybe an SSD for storing reference blocks and other data. The intelligentprocessing unit 910 performs processing functions such as deltaderivation, similarity detection, combining delta with reference blocks,managing reference blocks, executing cache management functionsdescribed herein, and managing meta data. The RAM cache 908 maytemporarily store reference blocks, deltas, and independent blocks foractive I/O operations. The HBA card 922 may be connected to the HDD 920through an HDD interface 914 using a suitable protocol such as SCSI,SATA, SAS, PATA, iSCSI, or FC.

A third embodiment is implemented at the HBA level but includes noonboard flash memory. An external SSD drive such as PCIe SSD, SAS SSD,SATA SSD, SCSI SSD, or other SSD drive may be used similarly to the SSDin the embodiment of FIG. 9. FIG. 10 depicts a block diagram describingthis implementation. The HBA 1020 has an intelligent processing unit1008 and a DRAM buffer 1004 in addition to the existing HBA controllogic and interfaces. The host system 1002 may be connected to thesystem bus 1014, such as PCI, PCI-Express, PCI-X, HyperTransport, orInfiniBand. The bus interface 1010 allows the HBA card 1020 to beconnected to the system bus 1014. The intelligent processing unit 1008performs processing functions such as delta derivation, similaritydetection, combining delta with reference blocks, managing referenceblocks, executing cache algorithms that are described herein, managingmeta data, and the like. The RAM cache 1004 temporarily stores deltasfor active I/O operations. The external SSD 1024 may be connected by anSSD interface 1022 to the HBA card 1020 for storage of reference blocksand other data.

While the above implementations can provide great performanceimprovements, all require redesigns of hardware such as a diskcontroller or an HBA card. A fourth implementation includes a softwareapproach using commodity off-the-shelf hardware. A software applicationat the device driver level controls a separate SSD drive/card, a GPU/CPUembedded controller card, and an HDD connected to a system bus. FIG. 11depicts a block diagram describing this software implementation. Thisimplementation leverages standard off-the-shelf hardware such as an SSDdrive 1114, an HDD 1118, and an embedded controller/GPU/CPU/MCU card1120. All these standard hardware components may be connected to astandard system bus 1122, such as PCI, PCI-Express, PCI-X,HyperTransport, InfiniBand, and the like. The software for this fourthimplementation may be divided into two parts: one running on a hostcomputer system 1102 and another running on an embedded system 1120. Onepossible partition of software between the host and the embedded systemmay be to have a device driver program 1110 capable of block leveloperation running on the host computer 1102 to perform meta datamanagement while interfacing with upper layer software (e.g. anoperating system 1108 or an application 1104), and the remainingsoftware functions running on the embedded system 1120. The softwarefunctions can be scheduled between host 1102 and the embedded system1120 so as to balance the loads of the embedded system 1120 and the hostsystem 1102 by taking into account all workload demand of the OS 1108,databases and applications 1104 etc. running on the host 1102.Typically, the embedded system 1120 performs computation-intensivefunctions such as similarity detections, compression/decompression, andhashing functions. The embedded system 1120 can off-load many functionsfrom the host to reduce its computation burden. A part of the system RAM1112 may be used to cache reference blocks, deltas, and other hot datafor efficient I/O operations and may be accessible to software modulesthat support this fourth embodiment.

A fifth embodiment for implementing the methods and systems describedherein utilizes a software module running entirely on the host computer.This software solution uses a part of system RAM as the DRAM buffer butassumes no additional hardware except for any type of off-the-shelf SSDand HDD devices. FIG. 12 describes this embodiment. A software module1210 runs at the device driver level such as a generic block layer, afilter driver layer, or any layer in the I/O stack. It controls anindependent SSD 1214 and an independent HDD 1218 that may be connectedto a system bus 1220. This implementation uses standard off-the-shelfhardware for the SSD 1214 and the HDD 1218. All these hardwarecomponents may be connected to a system bus 1220. The system bus 1220includes but is not limited to protocols such as PCI, PCI-Express,PCI-X, HyperTransport, InfiniBand, SAS, SATA, SCSI, PATA, USB, etc. Thesoftware implementing the fifth embodiment runs on the host computersystem 1202. A software module 1210 operates and communicates directlywith the SSD 1214 and the HDD 1218. The software module 1210 alsocontrols part of the system RAM 1212 as a cache to buffer referenceblocks, deltas, and independent blocks for efficient I/O operations. Thesoftware module 1210 also interfaces and communicates with upper layersoftware modules such as the OS 1208 and applications 1204 running onthe host 1202.

This fifth embodiment may be implemented without requiring hardwarechanges but it may use system resources such as the CPU, RAM, and thesystem bus. For I/O bound jobs, the CPU utilization can be very low andthe additional overhead caused by the software is expected to be small.This is particularly evident as processing power of CPUs increase muchmore rapidly than I/O systems. In addition, software implementations mayrequire different designs and implementations for different operatingsystems.

Referring to FIG. 13, a sixth embodiment for implementing the methodsand systems described herein also utilizes a software module runningentirely on the host computer. However, this software solution uses apart of system RAM as the DRAM buffer and optionally uses anoff-the-shelf SSD module if one is present. While this embodimentprovides significant performance increase to accessing data that isstored in a primary storage, this embodiment makes no changes to theprimary storage data. A software module 1310 runs at the device driverlevel such as a generic block layer, a filter driver layer, or any layerin the I/O stack. The software module 1310 controls part of the host RAM1312 and an optional SSD module 1314 to buffer reference blocks, deltas,and independent blocks for efficient primary storage 1318 operations.The software module 1310 also interfaces and communicates with upperlayer software modules such as the OS 1308 and applications 1304 runningon the host 1302.

Referring to FIG. 14, a primary storage directed write operation usingthis sixth embodiment is depicted. The host processor 1404 may instructthe primary storage 308 subsystem to perform a write of the data block408. This instruction is also delivered to the software module/driver1310 where it is determined if the data block 408 has a correspondingdelta 404 and reference block 402. If so, a new delta based ondifferences between the write data block 408 and the reference block 402is calculated and written to the delta buffer 1408 portion of the hostram 1402. If there is not already a corresponding delta 404 for the datablock 408, similarity of the data block to each of the cached referenceblocks may be checked using the similarity determination techniquesdescribed herein and a reference block 402 is selected. An originaldelta 404 is then generated and the delta 404 and meta data 1410 for thedata block 408 is generated and stored in the delta buffer 1408. Duringthe generation of the new delta or the original delta, if the resultingdelta is determined to be larger than a delta size threshold, the deltacompression algorithm may be terminated and an independent block 1412may be generated for storage in the delta buffer 1408. As can be seen inthe embodiment of FIG. 14, if SSD storage is available, reference blocks402, independent blocks 1412, and/or delta blocks 1414 may be stored inthe SSD.

Referring now to FIG. 15, a flow diagram of a primary storage directedwrite operation using the sixth embodiment is depicted. In this flowdiagram, a host may start a data block 408 host write operation at step1502. The software module/driver 1310 may search for a correspondingreference block in the cache (which may include the RAM buffer 1408and/or the SSD 304 from FIG. 14). Presuming that a reference block isfound, a new delta is generated in step 1504. As noted above for FIG.14, if a reference block is not found for the write data block 408, anoriginal delta may be generated based on a new reference block with themost similarity. If the generated new or the original delta is smallerthan a delta size threshold in step 1508 then flow proceeds to step 1510in which the delta is stored in cache, meta data for mapping the deltato the data block and the reference block is updated. If the new ororiginal delta is larger than the delta size threshold as determined instep 1508, flow proceeds to step 1512 in which the data block is storedin cache as an independent block and metadata to facilitate retrievingthis independent block is updated. Flow may proceed with step 1514 inwhich the software module 1310 determines if the generated delta can becombined with other deltas into a delta block that is suitable forstoring in SSD memory. If so, flow proceeds to step 1518 where a deltablock is generated and stored into the SSD memory (presuming that theSSD memory is available). Note that writing delta blocks from the RAMbuffer to SSD or primary storage may be based on LPU/CIP algorithmdescribed herein.

Referring now to FIG. 16, a block diagram of a primary storage readoperation following the sixth embodiment described herein above isdepicted. Processor 1404 may request access of a primary storage datablock 408. The request may be provided to the software module/driver1310 for executing the similarity-based delta compression techniquesdescribed herein. Software module/driver 1310 may read meta data 1410associated with the data block 408. The meta data 1410 may indicate thata delta 404 and a reference block 402 that are stored in cache (e.g. theRAM buffer 1408 of the host RAM 1402). The reference block and the deltamay be combined to generate the requested data block 408. Alternatively,the meta data 1410 may indicate that an independent block 1412 thatrepresents the requested data block 408 is available in the cache. Thesoftware module 1310 may access the independent data block and provideit to the processor 1404. If it is determined that a delta and anindependent block do not exist for the requested data block 408, theprimary storage 308 may be called upon to deliver the data block 408. Asdepicted in FIG. 16, if SSD storage is available, reference blocks 402,delta blocks 1414, and/or independent blocks 1412 may be stored in theSSD.

The host read operation depicted in the block diagram of FIG. 16 isshown as a flow chart in FIG. 17. A host processor may request a readdata block by starting a primary storage read operation at step 1702. Ifthe software module 1310 determines that a reference block exists forthe requested primary storage data block (such as by checking meta dataassociated with the primary storage data block) at step 1704, thecorresponding reference block and delta may be read from the cache andcombined to form the requested read data block in step 1708. If step1704 determines that a reference block does not exist for the requestedprimary storage data block, either an independent block is ready fromthe cache or the primary storage is relied upon to provide the requesteddata block in step 1710. The flow concludes in step 1712 in which therequested data block is provided to the requesting processor.

I/O scheduling for embodiments described herein may be quite differentfrom that of traditional disk storage. For example, the traditionalelevator scheduling algorithm for HDD aims at combining disk I/Os in anorder that minimizes seek distances on the HDD. In contrast, the methodsand systems herein facilitate changing I/O access scheduling toemphasize combining I/Os that may be similar to a reference block or maybe represented by deltas that are contained in one delta block stored inthe primary storage subsystem or a dedicated SSD storage module. To dothis scheduling, an efficient meta-data structure may be needed torelate LBAs of read I/Os to deltas stored in a delta block and to relateLBAs of write I/Os to reference blocks stored in SSD.

To serve I/O requests from the host, certain preferred embodiments use asliding window mechanism similar to the one used in the TCP/IP protocol.Write I/O requests inside the window may be candidates for deltacompression with respect to reference blocks and may be packed into onedelta block. Read I/O requests inside the window may be examined todetermine all those that were packed in one delta block. The windowslides forward as I/O requests are being served. Besides determining thebest window size while considering both reliability and performance,certain preferred embodiments may be able to pack and unpack a batch ofI/Os from the host so that a single HDD I/O operation generates manydeltas.

Identifying a reference block in SSD for each I/O may be a basicfunction of embodiments of the invention. For a write I/O, thecorresponding reference block, if present, needs to be identified fordelta compression. If the write I/O is a new write with no priorreference block, a new reference block may be identified that has themost similarity to the data block of the write I/O. For a read I/O, assoon as the delta corresponding to the read I/O is loaded, its referenceblock may be found to decompress to the original data block.

Quickly identifying reference blocks may be highly beneficial to theoverall I/O performance. In order to identify reference blocks quickly,reference blocks may be classified into three different categories. Thefirst category contains all reference blocks that have exactly the sameLBAs as deltas. These may be the data blocks originally stored in theSSD, but changes occur on these blocks during online operations such asdatabase transactions or file changes. These changes may be stored as apacked block of deltas to minimize random writes to SSD.

Because of content locality, the deltas may be expected to be small.Identifying this type of block may be straightforward with propermeta-data mapping of deltas to reference blocks.

The second category contains data blocks generated as results of virtualmachine creations. These blocks include copies of guest OS, guestapplication software, and user data that may be largely duplicates withvery small differences. Virtual machine cloning enables fast deploymentof hundreds of virtual machines in a short time. Different virtualmachines access their own virtual disk using virtual disk addresseswhile the host operating system manages the physical disk using physicaldisk address. For example, two virtual machines send two read requeststo virtual disk addresses V1_LBAO and V2_LBAO, respectively. These tworead requests may be interpreted by underlying virtual machine monitorto physical disk addresses LBAx and LBAy, respectively, which may beconsidered as two independent requests by a traditional storage cache.Embodiments of the invention relate and associate these virtual andphysical disk addresses by retrieving virtual machine relatedinformation from each I/O request. The requests with the same virtualaddress may be considered to have high possibility to be similar and maybe combined based on similarity. In the current example, block V1_LBAO(LBAx) is set as the reference block so the methods and systemsdescribed herein may be used to derive and keep the difference betweenV2_LBAO (LBAy) and VI_LBAO (LBAx) as delta.

The third category consists of data blocks that may be newly generatedwith LBAs that are not associated with any of the reference blocksstored in SSD. These blocks may be created by file changes, file sizeincreases, file creations, new tables, and so forth. While these newblocks may contain substantial redundant information compared to somereference blocks stored in the cache, quickly finding the correspondingreference blocks that have most similarity may allow best use of thedelta-compression and other techniques described herein. To support veryquick similarity detection, a new similarity detection algorithm isdescribed herein based on wavelet transform using GPU/CPU. While hashinghas been widely used to find identical blocks, the sub-signatures thatrepresent the combination of several hash values of sub-blocks may bemore appropriate for detecting similarity between two data blocks. Thefollowing paragraph describes briefly this similarity detectionalgorithm that may exploit modern CPU architectures.

The similarity of two blocks may be determined by the number ofsub-signatures that the two blocks share. A sufficient number of sharedsub-signatures may indicate that the two blocks are similar in content(e.g. they share many same sub-signatures). However, such contentsimilarity can be either an in-position match or an out-of-positionmatch where the position change is caused by content shifting (e.g.inserting a word at the beginning of a block shifts all remaining bytesdown by the word). To efficiently handle both in-position matches andout-of-position matches, embodiments use a combination of regular hashcomputations and wavelet transformation. Hash values for every threeconsecutive bytes of a block may be computed to produce a one bytesignature. A Haar wavelet transform may be also computed. The mostfrequently occurring sub-signatures may be selected along with a numberof coefficients of the wavelet transform for signature matching. In anexample, six of the most frequently occurring sub-signatures and threeof three wavelet transform coefficients may be selected. That is, ninesignature matching elements representing a block may be compared: sixsub-signatures and three coefficients of the wavelet transform. Hashvalues may be computed with more or fewer than three consecutive bytes.Similarly, more or fewer than six frequent sub-signatures may beselected. Likewise, more or fewer than three Haar wavelet coefficientsmay be selected.

The three coefficients of the wavelet transform may include one totalaverage, and the positions of the two largest amplitudes. The totalaverage coefficient value may be used to pick the best reference ifmultiple matches are found for the other eight signatures.

Consider an example of a 4 KB block. Embodiments of the invention firstcalculate the hash values of all sets of three consecutive bytes toobtain 4K-2 sub-signatures. Among these sub-signatures, the six mostfrequent sub-signatures may be selected together with the threecoefficients of the wavelet transform to carry out the similaritydetection. If the number of matches of two blocks exceeds seven, theymay be considered to be similar. Based on experimental observations,this position-aware sub-signature matching mechanism can recognize notonly shifting of content but also shuffling of contents.

Sub-signatures of a data block may also be computed using slidingtokens. The size of the token ranges from three bytes to hundreds ofbytes. The token slides one byte a time from the beginning to the end ofthe block. Hash values of each sliding token is computed using Rabinfinger print, Mersenne prime modulus, or random polynomials etc.Sampling or sorting techniques are used to select a few sub-signaturesof each block for similarity detection and reference selectionprocessing.

FIG. 18 shows a high level flowchart for similarity detection that maybe invoked periodically. For similarity detection upon an access to anew data block, similarity data (e.g. signatures, sub-signatures, andpotentially heatmap data) of a set of reference blocks are searched tofind a sufficiently similar reference block. Such a reference blockshould result in a delta that is less than a predefined delta sizethreshold as described herein. Once a suitable reference block is found,the new data block may be designated as an associate. Also, the delta,and similarity detection-related meta data are stored in a datastructure that facilitates rapid access to delta, reference, andindependent data block information.

For periodic similarity detection, the period length and the set ofblocks to be examined can be configured based on performancerequirements and the sizes of available RAM, SSD and primary storage ifit is available. For periodic similarity detection, after selection of aset of cached blocks at step 1802 to examine for similarity detections,popularity of each block may be computed at step 1804. Each block maythen be evaluated to determine its popularity. If the popularity of ablock exceeds a predefined and configurable threshold value checked instep 1808, the data block may be designated as a reference block in step1810 to be stored in the RAM or the SSD. If step 1808 determined thatthe similarity value of the two blocks is less than the threshold value,the process continues to other blocks through step 1812. The designatedreference block(s) from step 1810 may be stored in the cache andmetadata about the block may be updated to allow association ofremaining similar blocks for delta-compression. Finally, after all thedata blocks in the set may be compared, the heat map is cleared in step1818 to begin a new phase of sub-signature generation and blockpopularity accounting.

Referring to FIG. 19, a flowchart is depicted of cache managementactions that may be taken upon a new access to a data block notcurrently known to the cache management system (e.g. resulting from acache miss). The flow starts by loading the data block indicated by acache miss from primary storage (e.g. mass storage, SAN, and the like)at step 1902. The flow proceeds to step 1904 where sub-signatures of thenewly loaded data block are calculated. The sub-signatures are used in asearch of the currently known reference blocks to look for referenceblocks that include sub-signatures that match those generated in thisstep. The number of matching sub-signatures is compared to adelta-compression similarity threshold in step 1908. If the number ofmatching sub-signatures exceeds the similarity threshold, a candidatereference block is identified and flow proceeds to step 1910. If thenumber of matching sub-signatures does not exceed the similaritythreshold, flow proceeds to step 1912.

In step 1910, delta compression techniques, such as those describedherein may be used to perform delta compression of the newly loadedblock to determine the degree of similarity between the newly loadedblock and the identified reference block. The degree of similarity istested by comparing the size of the delta generated throughdelta-compression against a maximum difference threshold in step 1914.If the delta-compression result in a delta that is at least a small as adelta size threshold, the newly loaded block can be represented by acombination of the delta and a reference block so flow continues to step1918 in which the derived delta is stored in the cache system memory andcache management meta-data is updated.

If the delta-compression derived difference is larger than the deltasize threshold, then the block may be sufficiently different to warrantbeing maintained as an independent block and flow proceeds to step 1912.In step 1912, the newly loaded block is stored as an independent block(one that is not represented by a combination of deltas with respect toa reference block), and cache meta-data is updated.

Embodiments of the invention may attempt to store reference blocks inSSD that do not change frequently and that share similarities with manyother data blocks. Guidelines for determining what data to store in SSDand how often to update SSD may be established. Such guidelines maytradeoff size, cost, available SSD memory, application factors,processor speed(s), and the like. An initial design guideline may allowstoring the entire software stack including OS and application softwareas well as all active user data as base data (e.g. in the SSD or RAM).This may be quite feasible with today's large-volume and less expensiveNAND flash memories coupled with the fact that only a small percentageof file system data are typically accessed over a week. Data blocks ofthe software stack and base data may be reference blocks in SSD. Runtime changes to these reference blocks may be stored in compressed formin delta blocks in HDD. These changes include changes on file data,database tables, software changes, virtual machine images, and the like.Such changes may be incremental so they can be very effectivelycompacted in delta blocks. As changes keep occurring, incremental driftmay get larger and larger. To maintain high efficiency, data stored inthe SSD may be updated to avoid excessively large incremental drift.Each update may result in changes in SSD and HDD as well as associatedmetadata.

The next design decision may be the optimal block size of referenceblocks and delta blocks. Using larger reference blocks may reducemeta-data overhead and may allow more deltas to be covered by onereference block. However, if the reference block size is too large, itplaces a burden on the GPU/CPU for computation and caching. Similarly,large delta blocks allow more deltas to be packed in and potentiallyhigh I/O efficiency because one disk operation generates more I/Os (notethat each delta in a packed delta block represents one I/O block). Onthe other hand, it may be a challenge whether I/Os generated by the hostcan take full advantage of this large amount of deltas in one deltablock as discussed previously.

Another trade-off may be whether to allow deltas packed in one deltablock to refer to single reference block or multiple reference blocks inSSD. Using one reference block to match all the deltas in one deltablock allows compression/decompression of all deltas in the delta blockto be done with one SSD read. On the other hand, it may be preferablethat the deltas compacted in one delta block belong to I/O blocks thatmay be accessed by the host in a short time frame (temporal locality) sothat one HDD operation can satisfy more I/Os that may be in one batch.These I/O blocks in the batch may not necessarily be similar to exactlyone reference block for compression purposes. As a result, multiple SSDreads may be necessary to decompress different deltas stored in onedelta block. Fortunately, random read speed of SSD is so fast that itmay be affordable to carry out reference block reads online.

Some embodiments of the invention have a DRAM buffer that temporarilystores I/O data blocks including reference blocks and delta blocks thatmay be accessed by host I/O requests. This DRAM may buffer four types ofdata blocks: compressed deltas, data blocks for read I/Os afterdecompression, reference blocks from SSD, and data blocks of write I/Os.There may be several interesting trade-offs in managing this DRAMbuffer. The first interesting tradeoff may be whether compressed deltasare cached for memory efficiency, or whether decompressed data blocksare cached to facilitate high performance read I/Os. If compresseddeltas are cached, the DRAM can store a large number of deltascorresponding to many I/O blocks. However, upon each read I/O,on-the-fly computation may be necessary to decompress the delta to itsoriginal block. If decompressed data blocks are cached, these blocks maybe readily available to read I/Os but the number of blocks that can becached is smaller than caching deltas.

The second interesting tradeoff may be the space allocation of the DRAMbuffer to the four types of blocks. Caching large number of referenceblocks can speed up the process of identifying a reference block,deriving deltas upon write I/Os, and decompressing a delta to itsoriginal data block. However, read speed of reference blocks in SSD mayalready be very high and hence the benefit of caching such referenceblocks may be limited. Caching a large number of data blocks for writeI/Os, on the other hand, helps with packing more deltas in one deltablock but raise reliability issues. Static allocation of cache space todifferent types of data blocks may be simple but may not be able toachieve optimal cache utilization. Dynamic allocation, on the otherhand, may utilize the cache more effectively but incurs more overhead.

The third interesting tradeoff may be fast write of deltas toSSD/primary storage versus delayed writes for packing large number ofdeltas in one delta block. For reliability purposes, it may bepreferable to perform a write to SSD/primary storage as soon as possiblewhereas for performance purposes it may be preferable to pack as manydeltas in one block as possible before executing an SSD/primary storagewrite operation.

The computation time of Rabin fingerprint hash values is measured forlarge data blocks on multi-core GPU/CPUs. This computation is helpful inidentifying reference blocks in SSD. The times it takes to compute hashvalues of a data block with size of 4 KB to 32 KB may be in the range ofa few to tens of microseconds. In embodiments of the invention three ofthe most time-consuming processing parts have been implemented on theGPU/CPU.

The first part is the signature generation that includes hashingcalculations, sub-signature sampling, the Haar wavelet transform, andfinal selection of representative sub-signatures. As describedpreviously, groups of consecutive bytes may be hashed to derive adistribution of sub-signatures. This operation can be done in parallelby calculating all the hash values at the same time using multi threads.Sampling and selection can be done using random sample, sorting based onhistogram, or min wise independent selection.

The second part is the periodic Kmean computations to identifysimilarities among unrelated data blocks. Such similarity detection canbe simplified as a problem of finding k centers in a set of points. Theremaining points may be partitioned into k clusters so that the totalwithin a cluster sum of squares (TWCSS) is minimized. Multiple threadsmay be able to calculate the TWCSS for all possible partitioningsolutions at the same time. The results may be synchronized at the endof the execution, and the optimum clustering is a result. In the currentprototype implementation, Kmean computation was invoked periodically toidentify reference blocks to be stored in the cache.

The third part is delta compression and decompression. A ZDeltacompression algorithm or LZO compression algorithm may be used; howeveroptimization of delta codec is possible and may benefit from finetuning.

In order to see whether embodiments of the invention may be practicallyfeasible and provide anticipated performance benefits, aproof-of-concept prototype was developed using open source KernelVirtual Machine (KVM). The prototype represents only a partialrealization, using a software module, of the methods and systemsdescribed herein. The system is referred to as I-CASH (I-CASH is a shortname Intelligently Coupled Array of SSD and HDD).

The functions that the prototype has implemented include identifyingreference blocks in a virtual machine environment and using Kmeansimilarity detections periodically, deriving deltas using ZDeltaalgorithm for write IIOs, serving read IIOs by combining deltas withreference blocks, and managing interactions between SSD and HDD. Thecurrent prototype carries out the necessary computations using the hostCPU and uses a part of system RAM as the DRAM buffer of the I-CASH. AGPU was not used for computation tasks in the prototype. It is believedthat the performance evaluation using this preliminary prototypepresents a conservative result.

In order to capture both block level I/O request information and virtualmachine related information, the prototype module may be implemented inthe virtual machine monitor. The I/O function of the KVM depends on QEMUthat is able to emulate many virtual devices including virtual diskdrive. The QEMU driver in a guest virtual machine captures disk I/Orequests and passes them to the KVM kernel module. The KVM kernel modulethen forwards the requests to QEMU application and returns the resultsto the virtual machine after the requests are complete. The I/O requestscaptured by the QEMU driver are block-level requests of the guestvirtual machine. Each of these requests contains the virtual diskaddress and data length. The corresponding virtual machine informationmay be maintained in the QEMU application part. The invention embodimentof the prototype may be implemented at the QEMU application level andmay therefore be able to catch not only the virtual disk address and thelength of an I/O request but also the information of which virtualmachine generates this request. The most significant byte of the 64-bitvirtual disk address may be used as the identifier of the virtualmachine so that the requests from different virtual machines can bemanaged in one queue. If two virtual machines are built based on thesame OS and application, two I/O requests may be candidates forsimilarity detection if the lower 56 bits of their addresses areidentical.

The software module maintains a queue of disk blocks that can be one ofthree types: reference blocks, delta blocks, and independent blocks. Itdynamically manages these three types of data blocks stored in the SSDand HDD. When a block is selected as a reference, its data may be storedin the SSD and later changes to this block may be redirected to thedelta storage consisting of the DRAM buffer and the HDD. In the currentimplementation, the DRAM is part of the system RAM with size being 32MB. An independent block has no reference and contains data that can bestored either in the SSD or in the delta storage. To make an inventionembodiment work more effectively, a threshold may be chosen for deltablocks such that delta derivation is not performed if the delta sizeexceeds the threshold value and hence the data is stored as independentblock. The threshold length of delta determines the number of similarblocks that can be detected during similarity detection phase.Increasing the threshold may increase the number of detected similarblocks but may also result in large deltas limiting the number of deltasthat can be compacted in a delta block. Based on experimentalobservations, 768 bytes are used as the threshold for the delta lengthin the prototype.

Similarity detection to identify reference blocks is done in twoseparate cases in the prototype implementation. The first case is when ablock is first loaded into an invention embodiment's queue and theinvention embodiment searches for the same virtual address among theexisting blocks in the queue. The second case is periodical scanningafter every 20,000 I/Os. At each scanning phase, the inventionembodiment first builds a similarity matrix to describe the similaritiesbetween block pairs. The similarity matrix is processed by the Kmeanalgorithm to find a set of minimal deltas that are less than thethreshold. One block of each such pair is selected as reference block.The association between newly found reference blocks and theirrespective delta blocks is reorganized at the end of each scanningphase.

A prototype may be installed on KVM of the Linux operating systemrunning on a PC server that is a Dell PowerEdge T410 with 1.8 GHz XeonCPU, 2 GB RAM, and 160G SATA drive. This PC server acts as the primaryserver. An SSD drive (OCZ Z-Drive p84 PCI-Express 250 GB) is installedon the primary server. Another PC server, the secondary server, is DellPrecision 690 with 1. 6 GHz Xeon CPU, 2 GB RAM and 400G Seagate SATAdrive. The secondary server is used as the workload generator for someof the benchmarks. The two servers are interconnected using a gigabitEthernet switch. The operating system on both the primary server and thesecondary server is Ubuntu 8.10. Multiple virtual machines using thesame OS are built to execute a variety of benchmarks.

For performance comparison purpose, a baseline system is also installedon the primary PC server. The main difference between the base linesystem and a system implementing the methods and systems describedherein is the way the SSD and HDD are managed. In the baseline system,the SSD is used as an LRU disk cache on top of the HDD. In a systemimplementing the methods and systems described herein, on the otherhand, the SSD stores reference data blocks and HDD stores deltas asdescribed previously.

Appropriate workloads may be important for performance evaluations. Itshould be noted that evaluating the performance of embodiments of theinvention is unique in the sense that I/O address traces are notsufficient because deltas are content-dependent. That is, the workloadshould have data contents in addition to address traces. Because of thisuniqueness, none of the available I/O traces is applicable to theperformance evaluations. Therefore, seven standard I/O benchmarks thatare available to the research community have been collected as shown inTable 1.

TABLE 1 Standard benchmarks used in performance evaluation of I-CASH.Abbreviation Name Description RU RUBiS e-Commerce web server workload TPTPC-C Database server workload SM SPECmail2009 Mail server workload SBSPECwebBank Online banking SE SPECwebEcommerce Online store sellingcomputers SS SPECwebSupport Vendor support website SF SPECsfs2008 NFSfile server

The first benchmark, RUBiS, is a prototype that simulates an e-commerceserver performing auction operations such as selling, browsing, andbidding similar to eBay. To run this benchmark, each virtual machine onthe server has installed Apache, Mysql, PHP, and RUBiS client. Thedatabase is initialized using the sample database provided by RUBiS.Five virtual machines are generated to run RUBiS using the defaultsettings of 240 clients and 15 minutes running time.

TPC-C is a benchmark modeling the operations of real-time transactions.It simulates the execution of a set of distributed and on-linetransactions (OLTP) on a number of warehouses. These transactionsperform the basic database operations such as inserts, deletes, updatesand so on. Five virtual machines are created to run TPCC-UVAimplementation on the Postgres database with 2 warehouses, 10 clients,and 60 minutes running time.

In addition to RUBiS and TPC-C, five data intensive SPEC benchmarksdeveloped by the Standard Performance Evaluation Corporation (SPEC) havealso been set up. SPECMail measures the ability of a system to act as anenterprise mail server using the Internet standard protocols SMTP andIMAP4. It uses folders and message MIME structures that include bothtraditional office documents and a variety of rich media contents formultiple users. Postfix was installed as the SMTP service, Dovecot asthe IMAP service, and SPECmail2009 on 5 virtual machines. SPECmail2009is configured to use 20 clients and 15 minutes running time. SPECweb2009provides the capability of measuring both SSL and non-SSLrequest/response performance of a web server. Three different workloadsare designed to better characterize the breadth of web server workload.The SPECwebBank is developed based on the real data collected fromonline banking web servers. In an experiment, one workload generatoremulates the arrivals and activities of 20 clients to each virtual webserver under test. Each virtual server is installed with Apache and PHPsupport. The secondary PC server works as a backend application anddatabase server to communicate with each virtual server on the primaryPC server. The SPECwebEcommerce simulates a web server that sellscomputer systems allowing end users to search, browse, customize, andpurchase computer products. The SPECwebSupport simulates the workload ofa vendor's support web site. Users are able to search for products,browse available products, filter a list of available downloads basedupon certain criteria, and download files. Twenty clients are set up totest each virtual server for both SPECwebEcommerce and SPECwebSuppor for15 minutes. The last SPEC benchmark, SPECsfs, is used to evaluate theperformance of an NFS or CIFS file server. Typical file server workloadssuch as LOOKUP, READ, WRITE, CREATE, and REMOVE are simulated. Thebenchmark results summarize the server's capability in terms of thenumber of operations that can be processed per second and the I/Oresponse time. Five virtual machines are setup and each virtual NFSserver exports a directory to 10 clients to be tested for 10 minutes.

Using the preliminary prototype and the experimental settings, a set ofexperiments have been carried out running the benchmarks to measure theI/O performance of embodiments of the invention as compared to abaseline system. The first experiment is to evaluate speedups ofembodiments of the invention compared to the baseline system. For thispurpose, all the benchmarks were executed on both an embodiment of theinvention and on the baseline system.

FIG. 20 shows the measured speedups for all seven benchmarks. From thisfigure, it is observed that for 5 out of 8 benchmarks the methods andsystems described herein improve the overall I/O performance of thebaseline system by a factor of 2 or more with the highest speedup beinga factor of 4. In the experiment, 3 different SSD sizes were considered:256 MB, 512 MB, and 1 GB. It is interesting to observe from this figurethat the speedup does not show monotonic change with respect to SSDsize. For some benchmarks, large SSD gives better speedups while forothers large SSD gives lower speedups. This variation indicates apotential dependence on the dynamics of workloads and data content asdiscussed above.

While I/O performance generally increases with the increase of SSD cachesize for the baseline system, the performance change of the testedembodiment of the invention depends on many other factors in addition toSSD size. For example, even though there is a large SSD to hold morereference blocks, the actual performance of the tested embodiment mayfluctuate slightly depending on whether or not the system is able toderive a large amount of small deltas to pair with those referenceblocks in the SSD, which is largely workload dependent. Nevertheless,the tested embodiment performs constantly better than the baselinesystem with performance improvement ranging from 50% to a factor of 4 asshown in FIG. 20.

The speedups shown in FIG. 20 are measured using 4 KB block size forreference blocks to be stored in the SSD. This block size is also thebasic unit for delta derivations and delta packing to form delta blocksto be stored in the HDD. As discussed in the previous section, referenceblock size is a design parameter that affects delta computation andnumber of deltas packed in a delta block.

FIG. 21 shows speedups measured using a similar experiment but with an 8KB block size. Comparing FIG. 21 with FIG. 20, very small differenceswere noticed on overall speedup when an 8 KB block size is compared to a4 KB block size. Intuitively, large block size should give betterperformance than small block size because of the large number of deltasthat can be packed in a delta block stored in the HDD. On the otherhand, large block size increases the computation cost for deltaderivations. It is expected that the situation may change if a dedicatedhigh speed GPU/CPU is used for such computations.

To isolate the effect of computation times, the total number of HDDoperations of the tested embodiment and that of the baseline system weremeasured. The I/O reductions of the tested embodiment were thencalculated as compared to the baseline by dividing the number of HDDoperations of the baseline system by the number of HDD operations of thetested embodiment.

FIGS. 22 and 23 show the I/O reductions for all the benchmarks withblock size being 4 KB and 8 KB, respectively. It may be deduced fromthese figures that the tested embodiment reduces the number of HDDoperations to half at least for all benchmarks. This factor of two I/Oreduction did not directly double performance in terms of overall I/Operformance. This can be attributed to the computation overhead of thetested embodiment since the current prototype is implemented in softwareand consumes system resources for delta computations. This observationcan be further evidenced by comparing FIG. 22 with FIG. 23 where theonly difference is block size. With larger block size, the HDD disk I/Oreduction is greater than smaller block size because more deltas may bepacked in one delta block stored in the HDD. However, the overallperformance differences between these two block sizes, as shown in FIGS.20 and 15, are not as noticeable as I/O reductions.

From FIGS. 20 through 23 it is noticed that RUBiS benchmark performs thebest on the tested embodiment for all cases. To understand why thisbenchmark shows such superb performance, the I/O traces of thebenchmarks were analyzed. Analyzing the I/O traces unveiled that RUBiSbenchmark has 90% of blocks that are repeatedly accessed for at least 2times and 70% of blocks that are accessed for at least 3 times. Thishighly repetitive access pattern is not found in other 6 benchmarks. Forexample, 40% of blocks are accessed only once in the SPECmail benchmarkrun.

Because of time constraint, benchmark running time was limited in theexperiments. It might have been that the repetitive access pattern mayshow after a sufficiently long running time since such behavior isobserved in real world I/O traces such as SPC-1.

Besides I/O access patterns that affect performance of the testedembodiment, another factor impacting that performance is the percentageof I/O blocks that can find their reference blocks in SSD and can becompressed to small deltas with respect to their corresponding referenceblocks. FIG. 24 shows the percentage of independent blocks found in theexperiments. Recall that independent blocks are the I/O blocks that arestored in the traditional way because the tested embodiment may not findrelated reference blocks that produce a delta smaller than thepredefined threshold. From FIG. 24 it is observed that the testedembodiment is able to find over 50% of I/O blocks for delta compressionexcept for SPECsfs. The average delta sizes of the delta compression areshown in FIG. 25 for all the benchmarks. Clearly, the smaller the delta,the better the tested embodiment performs. Consistent with theperformance results shown in FIGS. 18 to 22, RUBiS benchmark has thelargest percentage of blocks that can be compressed and the least deltasize as shown in FIGS. 24 and 25. As a result, it shows the best I/Operformance overall.

The prototype of the tested embodiment uses a part of the system RAM (32MB) as the DRAM buffer that was supposed to be on a hardware controllerboard. As discussed previously, there are tradeoffs in managing thisDRAM buffer regarding what to cache in the buffer. To quantitativelyevaluate the performance impacts of caching different types of data, theI/O rate of the benchmarks was measured by changing the cache contents.FIG. 26 shows the measured performance results for four different cases:32 MB cache to store deltas, 32 MB cache to store data, 64 MB cache tostore data, and 128 MB to store data. As shown in the figure, cachingdelta is always better than caching data themselves even thoughadditional computations may be required. For the RUBiS benchmark whichshows strong content locality, using 128 MB RAM to cache data performsworse than using 32 MB to cache deltas. This clearly shows the benefitof the tested embodiment.

Finally, the average write I/O reductions of the tested embodiment werecompared to the baseline system. Recall that the preliminary prototypedoes not strictly disallow random writes to SSD as would have been doneby a hardware implementation of the tested embodiment. Some independentblocks that do not have reference blocks with deltas smaller than thethreshold value (768 byte in the current implementation) may be writtendirectly to the SSD if there is space available. Nevertheless, randomwrites to SSD may still be substantially smaller than the baselinesystem. FIG. 27 shows the ratio of the number of SSD writes of thebaseline system to the number of writes of the I-CASH. The writereduction ranges from a factor of two to an order of magnitude. Suchwrite I/O reductions imply prolonged life time of the SSD as discussedpreviously.

A novel data storage architecture has been presented exploiting the twoemerging semiconductor technologies, flash memory SSD and multi-coreGPU/CPU. The idea of the new disk I/O architecture may be intelligentlycoupling an array of SSDs and HDDs in such a way that read I/Os are donemostly in SSD and write I/Os to SSD are minimized and done in batches bypacking deltas derived with respect to the reference blocks.

By making use of the computing performance of modern GPUs/CPUs andexploiting regularity and content locality of I/O data blocks, certainpreferred embodiments of the invention replace mechanical operations inHDDs with high speed computations. A preliminary prototype realizingpartial functionality of the methods and systems described herein hasbeen built on Linux OS to provide a proof-of-concept. Performanceevaluation experiments using standard I/O intensive benchmarks haveshown great performance potential with up to 4 times performanceimprovement over systems that use SSD as a storage cache. It is expectedthat embodiments of the invention may dramatically improve data storageperformance with fine-tuned implementations and greatly prolong the lifetime of SSDs that are otherwise wearing quickly with random writeoperations.

Furthermore, the present methods and systems may exploit the everincreasing content locality found in a variety of primary storagesystems to minimize disk I/O operations that are still a significantbottleneck in computer system performance. A new cache replacementalgorithm called Least Popularly Used (LPU) may dynamically identify thereference blocks that may not only have the most access frequency andrecency but also may contain information that may be shared or resembledby other blocks being accessed. The LPU algorithms may also leverage themethods and systems described herein of caching reference blocks andsmall deltas to effectively service most disk I/O operations bycombining a reference block 402 with the corresponding delta inside thecache as opposed to going to the slow primary storage (e.g. a harddisk). The new cache replacement algorithm (LPU) may also be based onthe statistical analysis of frequency spectrum of both I/O addresses(e.g. LBAs) and I/O content. Applying a LPU algorithm may also increasea hit ratio of CPU-direct buffer caches greatly for a given cache sizethrough application of content locality considerations in the buffercache management algorithm. Therefore, embodiments of an LPU algorithmmay significantly improve diverse primary storage architectures (RAID,SAN, virtualized storage, and the like) by combining LPU techniques withthe various RAM/SSD/HHD cache embodiments described herein. In addition,applying aspects of LPU algorithms to buffer cache management maysignificantly improve hit ratios without changing or expanding buffercache memory or hardware.

In order to allow any of the caches described herein and elsewhere totake advantage of data access frequency, recency, and informationcontent characteristics, both access behavior and content signatures ofdata blocks being cached may be determined and tracked. For example,each cache block may be divided into S logical sub-blocks. Asub-signature may be calculated for each of the S sub-blocks. A twodimensional array of sub-signature related data, called a Heatmap, maybe maintained in an embodiment of an LPU algorithm. The Heatmap mayenable determining popularity of the cached data based on aspects oflocality (e.g. content locality, temporal locality, and the like).

FIG. 28 illustrates sub-block signatures and a Heatmap. The Heatmap ofFIG. 28 has S rows and Vs columns, where Vs is the total number ofpossible signature values for a sub-block. For example, if thesub-signature is 8 bits, Vs=256. Each entry in the Heatmap keeps apopularity value that may be defined as the number of accesses of thesub-block matching the corresponding signature value. In this example,each data block 2802 is divided into 8 sub-blocks and 8 correspondingsignature values are created. In this example, sub-signatures 55 and 0are shown. When a data block is accessed that contains a sub-signatureof 55 for its first logical sub block, the popularity valuecorresponding to column number 55 of the 1st row is incremented.Similarly, if a second sub block sub-signature of a data block is 0,then column number 0 of second row is also incremented. In this way, aHeatmap may keep popularity values of all sub-signatures of sub-blocks.

An alternate embodiment of a Heatmap may be organized as a twodimensional array that has columns that correspond to the number ofpossible signature values and rows that correspond to a number of timesthat each possible signature value has been accessed during apredetermined period of time.

To illustrate how a Heatmap may be organized and maintained as I/Orequests are issued, consider an example where each cache block isdivided into two sub-blocks and each sub-signature has only fourpossible values, i.e. Vs=4. The Heatmap of this example is shown inTable 2 below for a sequence of I/O requests accessing data blocks ataddresses LBA1, LBA2, LBA3, and LBA4, respectively. In this example, allof the possible contents of sub-blocks are depicted as A, B, C, and Dand the corresponding signature for each sub-block is a, b, c, and drespectively. A two dimensional embodiment of a Heatmap in this casecontains two rows corresponding to two sub-blocks of each data block andfour columns corresponding to the four possible signature values. Asshown in Table 2, all entries of the Heatmap are initialized to {(0, 0,0, 0), (0, 0, 0, 0)}. Whenever a data block is accessed, thepopularities of corresponding sub-signatures in the Heatmap areincremented. For instance, the first block has logical block address(LBA) of LBA1 with content (A, B) and corresponding signatures (a, b)for two sub-blocks. As a result of the I/O request, two popularityvalues in the Heatmap are incremented corresponding to the twosub-signatures, and the Heatmap becomes {(1, 0, 0, 0), (0, 1, 0, 0)} asshown in Table 2. After 4 requests of various data blocks, the Heatmapbecomes {(2, 1, 1, 0), (0, 1, 0, 3)} based on the accumulation ofsub-signature occurrences.

TABLE 2 The buildup of a Heatmap. Each block has 2 sub-blocksrepresented by 2 sub-signatures each having 4 possible values Vs = 4.Heatmap[0] Heatmap[1] I/O sequence Content Signature a b c d a b c dInitialized 0 0 0 0 0 0 0 0 LBA1 A B a b 1 0 0 0 0 1 0 0 LBA2 C D c d 10 1 0 0 1 0 1 LBA3 A D a d 2 0 1 0 0 1 0 2 LBA4 B D b d 2 1 1 0 0 1 0 3

The computation overhead to generate and maintain a Heatmap may besubstantially reduced over other data similarity counting techniques.Also, although Hashing may be a computation efficient technique todetect identical blocks, it may also lower the chance of findingsimilarity because a single byte change results in a totally differenthash value. Therefore, hashing by itself may not help in finding moresimilarities. On the other hand, an LPU algorithm may calculate thesecure hash value (e.g. SHA-1) of a data block to determine if a blockis identical to another.

In an alternate example of a two-dimensional Heatmap, taking a set of 4KB blocks divided into 512B sub-blocks with 8 bits sub-signature foreach sub-block, a Heatmap with 8 rows corresponding to 8 sub-blocks (4Kdivided by 512) and 256 columns corresponding to all of the possible8-bit signatures for a sub-block may be used. Each time a block is reador written, its 8 one-byte sub-signatures may be retrieved and the 8values of corresponding entries in the Heatmap (also known as popularityvalues) may be increased by one. Use of these frequency spectrum aspectsof content may differentiate LPU algorithms from conventional cachingalgorithms. As noted above, embodiments of an LPU algorithm may captureboth the temporal locality and the content locality of data beingaccessed by a host processor. If a block of the same address is accessedtwice, the increase of corresponding popularity value in the Heatmapreflects the temporal locality. On the other hand, if two similar blockswith different addresses are each accessed once, the Heatmap can catchthe content locality of these two blocks since the popularity values ofmatching sub-signatures are incremented in the Heatmap. In this way,popularity may be determined based on frequency and recency of asignature associated with active I/O operations. In an example, if asignature is shared by many active I/O blocks, then the signature ispopular. Block popularity may be based on block and sub-block signaturepopularity. A block that contains many popular signatures may beclassified as reference block and therefore may be cached and used withthe various delta generation and caching techniques described herein.Because many other active I/O blocks share content with this referenceblock, the net result is a higher cache hit ratio and more efficientdelta compression with respect to many other associated blocks thatshare such popular sub-signatures.

In order to capture the dynamic nature of content locality at runtime,LPU algorithms enable scanning cached blocks after a programmable numberof I/O requests. This number of I/O requests defines a scanning window.At the end of each scanning window, an LPU algorithm examines thepopularity values in the Heatmap and chooses the most popular blocks asreference blocks. An objective of selecting a reference block is toidentify a cached data block that may contain the most frequentlyaccessed sub-blocks so that many frequently accessed blocks sharecontent with it. The reference block may be selected such that thenumber of remaining blocks that have small differences (deltas) from thereference block may be maximized. In this way, more I/O requests may beserved by combining the reference block with small deltas. Once aHeatmap has been examined at the end of the scanning window, the Heatmapvalues may be reset to enable variations of popularity over time toinfluence the LPU algorithm and determination of reference blocks in thecache.

Table 4 shows the calculation of popularity values and the cache spaceconsumption using different choices of a reference block for the exampleof Table 2. The popularity value of a data block may be the sum of allits sub-block popularity values in the Heatmap. As shown in Table 3below, the most popular block is the data block at address LBA3 withcontent (A, D). Its popularity value is 5. Therefore, block (A, D) maybe chosen as the reference block. Once the reference block is selected,our LPU algorithm uses delta-coding to eliminate data redundancy. Theresult shows that using the most popular block (A, D) as the reference,cache space usage is minimum—about 2.5 cache blocks assumingnear-perfect delta encoding. Without considering content locality, aconventional Least Recently Used caching algorithm would need 4 cacheblocks to keep the same hit ratio. The space saved by applying an LPUalgorithm may be used to cache even more data.

TABLE 3 Selection of a reference block. The popularities of all blocksare calculated according to the Heatmap of Table3. Reference LBAs BlockPopularity LRU A B C D A D B D LBA1 A B 2 + 1 = 3 A B A B A B _ B A BLBA2 C D 1 + 3 = 4 C D C D C D C _(—) C _(—) LBA3 A D 2 + 3 = 5 A D _ DA _(—) A D A _(—) LBA4 B D 1 + 3 = 4 B D B D B _(—) B _(—) B D Cachespace 4 3.5 3 2.5 3

FIG. 29 shows the cache data content after selecting block (A, D) as thereference block. The LPU method facilitates dividing a cache into threeparts as shown in FIG. 29: a virtual block list 2902, data blocks 2904,and delta blocks 2908. The virtual block list 2902, referred to as anLPU queue, may store all the information of cached disk blocks with eachentry referencing and/or containing meta data, such as the address, thesignature, the pointer to the reference block, the type of block(reference, delta, independent) and the pointer to delta blocks for thecorresponding cached data block. However, the LPU queue may beconfigured to store pointers to virtual blocks rather than include thevirtual block data, thereby allowing a large number of virtual blocks tobe managed similarly to an LRU queue. The data pointer of a virtualblock may be NULL if the disk block represented by this virtual blockhas been evicted. The delta blocks 2908 may be managed in 64-bytechunks. A virtual block list entry may reference one or more deltablocks because incremental changes may have been made to the dataaddressed by the virtual block LBAx. As long as a virtual block listentry references sufficient delta blocks, a virtual block list entry maybe retained in the list even if its data block is evicted.Alternatively, as long as there is sufficient room in the delta block2908 part of the cache, a virtual block list entry may continue to beused to reference delta blocks even if the data block associated withthe virtual block list entry has been evicted from the cache because thedata block can be constructed from the various referenced delta blocksand a corresponding reference block.

A virtual block list, VBL for short, may be used with an LPU algorithmfor read and for write requests. Generally upon either a read or writerequest, the LBA is looked up in the VBL. If it is found, then the typeof block is determined from meta data in the corresponding VBL entry.Subsequent actions are generally based on the type of block and the typeof request (read or write).

For a read operation, the following actions are available:

Type=Independent—retrieve the data based on the LBA pointer in the VBL

VBLType=Unmodified Reference—retrieve the data based on the LBA pointerin the VBL

Type=Delta or Reference that has been modified—retrieve the delta andthe reference block and generate the requested data

For a write operation, the following actions are available

Type=Independent—generate a delta and update meta data in the VBL entrythat indicates this is a changed block with a delta

VBLType=Reference—generate a delta and update meta data in the VBL entrythat indicates this is a changed reference block with a delta

Type=Delta—generate a new delta and update meta data in the VBL entry orchange the type to Independent if the delta is too large

In the embodiment of FIG. 30, cached pages may be classified into threedifferent categories, Delta, Reference, and Independent pages. Whenthese three categories are targeted for SSD Storage a technique calledDRIPStore may enable making best use of high read performance of an SSDwhile also minimizing SSD write operations. Referring to FIG. 30, a pairof block diagrams showing a read and write process associated with aDRIPStore technique as described herein (that may also exploit contentlocality in optimizing SSD storage design). A reference page categoryfor DRIPStore may be defined as described elsewhere herein and/or maycomprise the pages that are popular at least because the differences oftheir content to many other pages can be described by generally smalldeltas. A delta page category for DRIPStore may be defined as acompacted block of many small deltas and as described elsewhere herein.An independent page category for DRIPStore may comprise the remainingpages that may not share enough similarity with reference pages. Suchpages may be called independent pages. A DRIPStore approach may treatpages categorized as Reference pages as read-only which is suitable forstorage in RAM and SSD. A DRIPStore approach may also attempt tominimize writes to the SSD by writing only compacted delta pages to SSDor to another portion of cache memory, rather than writing individualdeltas to SSD. Each compacted delta page may hold a log or otherdescription of many deltas. Because of potentially strong content accessregularity and/or content locality that may exist in data blocks, acompacted or packed delta page may contain metadata describing apotentially large number of small deltas with respect to referencepages, thereby reducing write operations in the SSD greatly. Embodimentsof a DRIPStore method may perform similarity detection, deltaderivations upon I/O writes, combining delta with reference pages uponI/O reads, and other necessary functions for interfacing the storage tothe host OS.

A delta that may be stored in a delta page may be derived at run timerepresenting the difference between the data page of an active I/Ooperation and its corresponding reference page stored in the RAM or SSD304. Referring now to DRIPStore write flow 3002 of FIG. 30, upon an I/Owrite, a DRIPStore process may identify a reference page in the SSD 304that corresponds to the desired I/O write page and may compute the deltawith respect to the reference page. Similarly in a DRIPSTORE read flow3004, upon an I/O read, the data block that corresponds to the desiredI/O read page may be returned by combining a delta for the I/O read pagewith its corresponding reference page. Since deltas may be small due todata I/O regularity and content locality, the deltas may be stored in acompact form and consolidated in to a packed delta page so that onewrite to the SSD 304 may satisfy tens or even hundreds of desired writeI/Os. A goal of applying DRIPStore may be to convert the majority ofprimary storage write I/Os to I/O operations involving mainly SSD 304reads and delta computations. Therefore, DRIPStore may take fulladvantage of the SSD 304's fast read performance and may avoid its poorerase/write performance. Further, at least partly because of 1) highspeed read performance of reference pages stored in the RAM and the SSD304, 2) a potentially large number of small deltas packed in one deltapage, and 3) high performance CPUs/GPUs, embodiments of DRIPStore may beexpected to improve SSD I/O performance greatly.

A component of the DRIPStore design may be to identify reference pages.In order to identify reference pages quickly, reference pages mayfurther be divided into at least two different categories. The firstreference page category may contain reference pages that may haveexactly the same LBAs as deltas. An example of a reference page in thisfirst category is a data block that has been modified since it wasdesignated as a reference block; therefore while the reference block maystill be useful to the caching system, the physical data to be stored inprimary storage requires this reference page to be combined with a deltapage. The second category may consist of data blocks that may be newlygenerated and may have LBAs that do not match any one of the referencepages stored in the SSD 304.

To facilitate similarity detection of blocks and/or reference blocks,for each data block, the DRIPStore process may compute blocksub-signatures. Generally, a one byte or a few bytes signature may becomputed from several sequential bytes of data in the data block 408.Two pages may be considered similar if they share a minimum number ofsub-signatures. However, content similarity between two data blocks maybe an in-position match or an out-of-position match which may be causedby content shifting (e.g. inserting a word at the beginning of a blockshifts all remaining bytes down by the word). To efficiently handle bothin-position matches and out-of-position matches, a DRIPStore process mayuse a combination of sub-signatures (e.g. such as those describedelsewhere herein) and a histogram of a data page/block. Hash values forevery k consecutive bytes of a page may be computed to produce 1-byte ora few bytes sub-signatures. Considering a conventional byte size ofeight bits, there are 256 possible values for each sub-signature if thesub-signature size is 1-byte. A histogram of all 1-byte hash values in adata page may be summarized into 256 bars corresponding to thesepossible values of sub-signatures. If sub-signatures include more orless than eight bits, the number of possible values of reachsub-signature may be greater or fewer than 256. From this histogram, onemay determine the frequency of occurrences of each sub-signature valuein the block. Subsequently, the most frequently occurring sub-signaturesmay be used to find matches with the most frequent sub-signatures ofother pages. The total number of occurrences of each sub-signature inthe histogram may be accumulated across all blocks considered, resultingin a list of the degrees of sharing of each sub-signature among all theblocks considered. These degrees of sharing may be used as weights tocompute a final popularity value. The block or blocks with the largestpopularity value(s) may be selected as one or more reference pages.

Referring to FIG. 31, a reference page selection process is illustrated.In order to see how the similarity detection algorithm works, considerthe following example. Four blocks may be considered to determine whichone should be the reference page. Further, for simplicity ofexplanation, each sub-signature may be any one of 5 different values: 0,1, 2, 3, and 4. After computing all sub-signatures in each of the 4blocks, A, B, C, and D, a block histogram 3102 may be derived for eachblock A, B, C, and D, respectively. Note that there are only 5 bars ineach histogram corresponding to the five possible signature values, 0,1, 2, 3, and 4, respectively. In data block A, the most frequentsub-signature is 2 and the second most frequent is 4. Similarly, the twomost frequent sub-signatures in block B are 1 and 4. From these fourblock histograms 3102, the two most frequent sub-signatures for eachdata block may be picked to create a block histogram subset 3104. It maybe easily seen from the block histogram subset 3104 that among the 4data blocks, sub-signature 4 appears three times (degree of sharing is3), sub-signature 2 appears two times (degree of sharing is 2), andsub-signature 0, 1, and 3 appear one time each (degree of sharing is 1).After deriving these degrees of sharing, popularity of each block may becomputed by accumulating the degrees of sharing matching each of thesub-signatures in the block diagram subset 3104. In this example, thepopularity of block A is 2+3=5 because the degree of sharing ofsub-signature 2 is 2 and the degree of sharing of sub-signature 4 is 3.Both signatures 2 and 4 appeared in the block histogram subset 3104 forblock A. Similarly, the popularity of block B is 1+3=4, the popularityof block C is 1+2=3, and the popularity of block D is 1+3=4. Block A hasthe highest popularity value which is 5 and therefore is selected as thereference page depicted in 3108. Blocks B, C, and D all share somesub-signatures with block A, implying that A is resembled by all otherthree blocks and these three blocks may be compressed with delta codingusing block A as the reference data.

An exemplary implementation of DRIPStore may compute 1-bytesub-signatures of every 3 consecutive bytes in a data block, i.e. k=3.It may then select the 8 most frequent sub-signatures for signaturematching, i.e. f=8. In an example, for a 4 KB block, the DRIPStoreprocess may first calculate the hash values of all 3 consecutive bytesto obtain 4K-2 sub-signatures. If the number of matches between a blockand the reference exceeds 6, this block may be associated with thereference. Based on experimental observations, this sub-signature withposition mechanism may recognize not only shifting of content but alsoshuffling of contents.

The data blocks to be examined for similarity detection may bedetermined based on performance and overhead considerations. Contentlocality may exist in a storage system both statically and dynamicallyand the data redundancy may be found in one of two ways. First, ascanning thread may be used to scan the storage device periodically. Astatic scan may be easy to implement since data may be fixed and thescan may achieve a good compression ratio by searching for the bestreference blocks. However, a static scan may read data from differentstorage devices and the similar blocks found may not necessarily havetight correlation other than content similarity. The DRIPStore algorithmmay take a second approach which may identify similar blocks online fromthe data blocks already loaded in a cache. For a write I/O, acorresponding reference block for delta compression may be found. If thewrite I/O were a new write with no prior reference block, a newreference block may be identified for that write I/O. For a read I/O, assoon as the delta corresponding to the read I/O may be loaded, areference block may be found to decompress to the original data block.

An alternative cache management algorithm that may take advantage of thedelta compression and other methods described herein may be referred toas conservative insertion and promotion (CIP). FIG. 32 illustrates ablock diagram of a CIP list. The CIP may keep an ordered list of cacheddata pages similar to the LRU list in traditional cache designs. Thisordered list of cached pages may be referred to as a CIP-List 3200 inFIG. 32. However, instead of ordering the CIP-List 3200 based on accessrecency, CIP may conservatively insert a newly referenced page towardthe lower end of the CIP-List 3200 and may gradually promote the page inthe CIP-List 3200 based on re-reference occurrence metrics. An aspect ofthe CIP cache replacement algorithm may be to maintain the CIP-List 3200that may include a RAM sub-list 3202, an SSD sub-list 3204, and acandidate sub-list 3208 as shown in FIG. 32. Upon the first reference toa page, the reference may be inserted in the candidate sub-list 3208 andmay gradually be promoted to the SSD sub-list 3204 and the RAM sub-list3202 as re-references to the page occur. As a result of suchconservative insertion and promotion, a CIP cache management algorithmmay filter out sweep accesses to sequential data without negativelyimpacting the cached data while conservatively caching random accesseswith higher locality. The CIP-List 3200 may implicitly keep accessfrequency information of each cached page without large overhead ofkeeping and updating frequency counters. In addition, the CIP mayclearly separate read I/Os from write I/Os by sending a batch of readonly I/Os or write only I/Os to an SSD NCQ (native command queue) or SQ(submission queue) to maximize the internal parallelism and pipeliningoperations typically found with SSD storage devices 304.

The CIP-List 3200 may be a linked list that may contain meta dataassociated with cached pages such as pointers and LBAs. Typically, eachnode in the list may need tens of bytes resulting in less than 1% spaceoverhead for page size of 4 KB. In addition to a head pointer 3210 and atail pointer 3212 of the linked list, the CIP adds a SSD pointer 3214 topoint at the top of the SSD sub-list 3204 and the candidate pointer 3216to point at the top of candidate sub-list 3208, respectively, as shownin FIG. 32.

Referring to FIG. 33, a block diagram of the system including the RAMlayout for RAM cache is illustrated. In an example, variable LR may bethe amount of the RAM controlled by the RAM sub-list 3202, LS may be theamount of the SSD controlled by the SSD sub-list 3204, and LC may be theamount of storage controlled by the candidate sub-list 3208. Further,variable B may be the block size of the SSD 304 in terms of number ofpages. The size of the RAM that the CIP may manage may be computed asLR+LC+B.

There may be three types of replacements in the CIP algorithm. A firstreplacement may include replacing a page from the RAM sub-list 3202 tothe SSD sub-list 3204. A second replacement may include replacing a pagefrom the SSD sub-list 3204 to the HDD 308. A third replacement mayinclude replacing a candidate page from the candidate sub-list 3208 toHDD 308. All these replacements may happen at or near the bottom of eachsub-list, similar to the LRU list. That is, the higher position a pageis in the CIP-List 3200, the more important the page may be and the lesslikely that it may be replaced. The CIP algorithm may conservativelyinsert a missed page at the lower part of the CIP-List 3200 and may letit move up gradually as re-references to the page occur. This mayfacilitate managing a multi-level cache that may consider recency,frequency, inter-reference interval times, and bulk replacements in theSSD 304.

In embodiments, page reference recency information may be used formanaging the cache for many different workloads. This may be why an LRUalgorithm has been popular and used in many cache designs. The CIPalgorithm may maintain the advantages of LRU design by implementing thecandidate sub-list 3208, RAM sub-list, or SSD sub-list as a LRU list.The candidate sub-list 3208 may contain pages that may be brought intothe RAM upon misses or it may contain only metadata of pages that havebeen missed once or only a few times even though the data is not yetcached. Upon a miss, the metadata of the missed page may be inserted ator near the top of the candidate sub-list 3208 and may be given anopportunity to show its importance to stay in the candidate-list untilthe LCth miss before it may be replaced. If it gets re-referenced duringthis time, it may be promoted to the top or at least near the top of theRAM sub-list 3202. Pages at the bottom of the RAM sub-list areaccumulated to form a batch to be written to the SSD 304 at which timetheir meta data is placed in the SSD sub-list 3204. The number ofre-references, maximum time required between re-references, and otheraspects that may impact a decision to promote a page within the CIP-list3200 may be tunable. In this way a page may get promoted if it isre-referenced only twice within a predetermined period of time or it mayrequire several re-references within an alternate predetermined periodof time to be tagged for promotion. A promotion algorithm may alsodepend on block size versus I/O access size so that even when an 8Kblock is accessed twice due to the I/O access size being 4K, a 4K pagestored in the Candidate sub-list may not be promoted upon the secondaccess to the candidate block to retrieve the second 4K page of the 8Kblock. Since the SSD 304 favors batch writes, the SSD write may bedelayed until B such pages have been accumulated on top of the SSDsub-list 3208. During this waiting period, if the page is re-referencedagain, it may be promoted to the RAM sub-list 3202 becauseinter-reference interval time of this page is small showing theimportance of the page indicates that it should be cached in the RAM.Therefore, the CIP-List 3200 may automatically maintain both recency andinter-reference recency information of cached pages taking advantages ofboth LRU and LIRS cache replacement algorithms.

In order to take into account reference frequency information inmanaging cache replacement, a new page to be cached in the RAM cache maybe inserted at the lower part (IR) 3218 of the RAM sub-list 3202 and mayget promoted one position up in the list upon each reference or upon aconfigurable number of references. Similarly, in the SSD sub-list 3204,any reference (or configurable number of references) may promote thereferenced page up by one position (or a configurable number ofpositions) in the CIP-List 3200. As a result of such insertion andpromotion policy, the relative position of a page in the CIP-List 3200may approximate the reference frequency of the page. Frequentlyreferenced pages may be unlikely to be evicted from the cache becausethey may be high up in the CIP-List 3200. For the RAM sub-list 3202, IR3218 may be a tunable parameter that may determine how long a newlyinserted page may stay in the cache without being re-referenced. Forexample, if IR 3218 is at the top of the CIP-List 3200, it is equivalentto LRU. If IR 3218 is at the bottom of the CIP-List 3200, the page maybe replaced upon next miss unless it is re-referenced before the nextcache miss. Generally, IR 3218 may point at the lower half of the RAMsub-list 3202 so that a new page may need to earn enough promotioncredits (e.g. have a high reference frequency) to move to the top andyet it may be given enough opportunity to show its importance before itis evicted. For the SSD sub-list 3204, insertion may always happen atthe top of the CIP-List 3200 where B pages may be accumulated to bewritten into the SSD 304 in batches. Once the recently added B pages arewritten into the SSD 304, their importance may depend on their referencefrequency since each time a page is referenced its position in the CIPlist may be promoted further up the list. The pages at the bottom of thelist may not have been referenced for a very long time and hence maybecome candidates for replacement when the SSD 304 is full. The CIP maytry to replace these pages in batches to optimize the SSD 304performance.

In addition to being able to taking into account recency, frequency, andinter-reference recency, the CIP algorithm may help avoid the impact ofmass storage scans and other types of mass storage sweep accesses oncached data and may be able to automatically filter out large sequentialaccesses so that they may not be cached in the SSD 304. This may be doneby the candidate sub-list 3208. Pages in a scan access sequence may notmake to the RAM sub-list or the SSD sub-list 3204 if they are notre-referenced and therefore may be replaced from the candidate bufferbefore they can be cached in the RAM or the SSD 304. Pages belonging toa large sequential scan accesses may be easily detected by comparing theLBA of a node in the candidate list and the LBAs of current/subsequentI/Os and using a threshold counter. In an embodiment, for cache hits,the algorithm may work in the following manner. If the referenced page,p, is in the RAM sub-list 3202 of the CIP-List 3200, p may be promotedby one position up if it is not already at the top of the CIP-List 3200.Upon a read reference to page p that may be in the SSD sub-list 3204 ofthe CIP-List 3200, p may be promoted by one position up if it is notalready among the top of B+1 pages in the SSD sub-list 3204. If p is oneof the top B+1 pages in the SSD sub-list 3204, p may be inserted at theIR position of the RAM sub-list 3202. Further, if the size of the RAMsub-list 3202 is LR at time of the insertion, the page at the bottom ofthe RAM sub-list 3202 may be demoted to the top of the SSD sub-list 3204and its corresponding data page may be moved from the RAM cache to theblock buffer to make room for the newly inserted page. The block counterin the SSD pointer may be incremented. If the counter reaches B,SSD_Write may be performed.

Upon a write reference to page p that is in the SSD sub-list 3204 ofCIP-List 3200, p may be removed from the SSD sub-list 3204 and insertedat the IR 3218 position of the RAM sub-list 3202. If the size of the RAMsub-list 3202 is LR at time of the insertion, the page at the bottom ofthe RAM sub-list 3202 may be demoted to the top of the SSD sub-list 3204and its corresponding data page may be moved from the RAM cache to theblock buffer to make room for the newly inserted page. The block counterin the SSD pointer may be incremented. If the counter reaches B,SSD_Write may be performed. In addition, if the referenced page, p, isin the candidate sub-list 3208 of CIP-List 3200, p may be inserted atthe top of the SSD sub-list 3204 and the corresponding data page may bemoved from the candidate buffer to the block buffer. The counter in theSSD pointer may be incremented. If the counter reaches B, SSD_Write maybe performed.

In another embodiment, for cache misses, the algorithm may work in thefollowing manner. If RAM cache is not full, the missed page p may beinserted at the top of the RAM sub-list 3202 and the corresponding datapage is cached in the RAM cache. If RAM cache is full, the missed page pmay be inserted at the top of the candidate sub-list 3208 and thecorresponding data page may be buffered in the candidate buffer or notcached at all. If the candidate buffer is full, the bottom page in thecandidate sub-list 3208 may be replaced to make room for the new page.

An SSD_Write may proceed as follows. If SSD is full, i.e. the SSDsub-list 3204 size equals LS, the CIP algorithm may destage the bottom Bpages in the SSD sub-list 3204 to the HDD 308. Only dirty destaged pagesneed to be read from the SSD 304 and written to HDD 308. Next, the CIPalgorithm may perform SSD writes to move all dirty data pages in theblock buffer to the SSD 304 followed by clearing the block buffer andthe block counter in the SSD pointer of the CIP-List.

Similarly, the candidate list may be a linked list or a simple table(array structure). The table may be hashed by using LBAs. Each entry maykeep a counter to count a number of cache misses that have occurredsince the entry was added to the candidate list so that thecorresponding data may be promoted to be cached once its counter exceedsa threshold. Exceeding such a threshold may indicate that data in thecache is stale and therefore performance may be improved by promotingcandidate data to the cache to replace stale data. Each entry may alsobe configured with a timer that impacts a re-reference counter for theentry. The re-reference counter may be reset to 0 once the timeinterval, determined by the timer, between two consecutive accesses(successive re-references) to the same block exceeds a predeterminedvalue. This interval between references may be calculated on each I/Oaccess to the same block by subtracting the current I/O accesstime-of-day and previously stored access time-of-day value in thecorresponding table entry.

Each sub-list of the CIP-list 3200 may include some overlapping pages.In an example, some of the pages in the RAM-list may also exist in theSSD list because a page in the SSD may have been promoted to the RAM andthe page in SSD may be unaffected until other pages are promoted to theSSD-sublist. This may not pose any significant problem because a RAMlist may be checked for presence of a page before an SSD list ischecked.

Referring to FIG. 34, a method of compression/de-duplication in a cachesubsystem of a data storage system that facilitates line-speed,software-based, low CPU-overhead, block level, pre-cachesimilarity-based delta compression is presented. Signatures as describedherein are computed for at least one data block 3402 (DBn) and at leastone reference block 3404 (RBn). In the embodiment of FIG. 34, bothreference block signatures 3408 (RSx) and data block signatures 3410(DSx) are computed based on three or more adjacent bytes in therespective block. A plurality of data block signatures (DSx) andreference block signatures (RSx) are generated and aggregated 3412 tofacilitate comparison 3414. Various techniques for aggregation aredescribed herein and any such technique may be applicable in theembodiment of FIG. 34. Comparing reference block signatures (RSx) withdata block signatures (DSx) may result in determining data in the datablock 3402 that is similar to the reference block (Similarity 3418).From this determination of similarity, differences 3420 may also bedetermined and those differences 3420 may be made available or storingin a cache as cache data 3422. This cache data 3422 may be packed into apacked cache block 3424 prior to being stored in a data cache.

Referring to FIG. 35, a method of compression/de-duplication in a cachesubsystem of a data storage system that facilitates line-speed,software-based, low CPU-overhead, block level, pre-cachesimilarity-based delta compression that is similar to the method of FIG.34 is presented. Signatures as described herein are computed for atleast one data block 3502 (DBn) and at least one reference block 3504(RBn). In the embodiment of FIG. 35, both reference block signatures3508 (RSx) and data block signatures 3510 (DSx) are computed based onthree or more adjacent bytes in the respective block. A plurality ofdata block signatures (DSx) and reference block signatures (RSx) aregenerated and aggregated using a heatmap 3512 as described herein tofacilitate calculating popularities of signatures 3514. The popularityvalue of each signature is updated upon each I/O. Accumulatingpopularity values of data block signatures (DSx) based on a heatmap 3512may facilitate determining which data block 3502 has sufficientpopularity to be used as a reference block (Similarity 3518). Likewisethrough determination of similarity, differences 3520 may also bedetermined and those differences 3520 may be made available or storingin a cache as cache data 3522. This cache data 3522 may be packed into apacked cache block 3524 prior to being stored in a data cache.

Referring to FIG. 36, a method of storing data in a cache memory of adata storage system that is capable of similarity-based deltacompression is presented. In the embodiment of FIG. 36, a cache systemthat is capable of similarity-based delta compression 3602, such as byway of example those depicted in FIGS. 34 and 35 may choose among aplurality of types of data blocks to determine data to be stored in acache memory system 3612. In the example of FIG. 36, thesimilarity-based delta compression capable cache system 3602 may receiveany number of reference blocks 3604, packed delta blocks 3608,frequently accessed blocks 3610, or other types of data for caching. Thesystem may apply the various techniques described herein to determine alocation for storing the received data. The various techniques includewithout limitation, signature based comparison, similarity-based deltacompression, content locality, temporal locality, spatial locality,signature popularity, block popularity, sub-signature frequency,sub-signature popularity, conservative insertion and promotion, locationof similar data blocks, type of data block, and the like. Based on thedetermination of a location for storing the received data, the system3602 may store any of the received reference blocks, packed deltablocks, and frequently accessed blocks in any portion of the cachememory 3612.

Referring to FIG. 37, a method of differentiated data storage in a cachememory system 3700 that comprises at least two different types of memoryis presented. In the method of FIG. 37, data placement of referenceblocks 3702 and difference data 3704 representing differences betweenreference blocks 3702 and data blocks may be determined. Referenceblocks 3702 may be received and stored in a first portion 3714 of acache data storage system 3710. Difference data 3704 representingdifferences between reference blocks 3702 and data blocks may beprovided to the cache system 3700 as a packed delta block 3708 forstorage in a second portion 3712 of the cache memory 3710 that does notcomprise SSD memory. Although the embodiment of FIG. 37 depicts thefirst portion 3714 as SSD type memory, this first portion may be SSD,RAM, HDD, or any other type of memory suitable for high performancecaching. Also, although the embodiment of FIG. 37 depicts the secondportion 3712 as RAM type memory, the second portion may be RAM, HDD orany other type of memory that is suitable for high performance cachingexcept for SSD type memory.

Referring to FIG. 38, a method of caching data based on at least one ofdata content locality, spatial locality, and data temporal locality ispresented. Data may be presented to a cache system that is capable ofdetermining content locality, spatial locality and/or temporal localityof the data. Based on the determined content locality, spatial localityand/or the determined temporal locality, data may be placed in variousportions of a cache memory system, such as HDD portion, SSD portion, RAMportion, and the like. In the example of FIG. 38, data 3802A and data3802B may be presented to a cache memory system that is capable ofdetermining content, spatial and/or temporal locality of the data.Determined content, spatial, and/or temporal locality 3808A of data3802A may indicate that data 3802A may be suitable for being stored in aRAM 3804A portion of a cache 3804. Likewise, determined content spatial,and/or temporal locality 3808B of data 3802B may indicate that data3802B may be suitable for being stored in an SSD 2904B portion of acache 3804. Determination of which portion of cache 3804 to use forstoring data 3802A or 3802B may be based on the methods and systemsdescribed herein for spatial, temporal and/or content locality-basedcaching. Further in an example, data that has any combination of highspatial, temporal or content locality may be stored in RAM or SSD,whereas data that has average spatial, temporal and content locality maybe stored in SSD, HDD or another portion of cache 3804 or may not bestored in the cache 3804 at all. Although content, spatial, and temporallocality are used to indicate which portion of a cache is suitable forstoring data, other techniques described herein may also be used toindicate which portion of a cache is suitable for storing data.

The methods and systems described herein may be deployed in part or inwhole through a machine that executes computer software, program codes,and/or instructions on a processor. The processor may be part of aserver, client, network infrastructure, mobile computing platform,stationary computing platform, or other computing platform. A processormay be any kind of computational or processing device capable ofexecuting program instructions, codes, binary instructions and the like.The processor may be or include a signal processor, digital processor,embedded processor, microprocessor or any variant such as a co-processor(math co-processor, graphic co-processor, communication co-processor andthe like) and the like that may directly or indirectly facilitateexecution of program code or program instructions stored thereon. Inaddition, the processor may enable execution of multiple programs,threads, and codes. The threads may be executed simultaneously toenhance the performance of the processor and to facilitate simultaneousoperations of the application. By way of implementation, methods,program codes, program instructions and the like described herein may beimplemented in one or more thread. The thread may spawn other threadsthat may have assigned priorities associated with them; the processormay execute these threads based on priority or any other order based oninstructions provided in the program code. The processor may includememory that stores methods, codes, instructions and programs asdescribed herein and elsewhere. The processor may access a storagemedium through an interface that may store methods, codes, andinstructions as described herein and elsewhere. The storage mediumassociated with the processor for storing methods, programs, codes,program instructions or other type of instructions capable of beingexecuted by the computing or processing device may include but may notbe limited to one or more of a CD-ROM, DVD, memory, hard disk, flashdrive, RAM, ROM, cache and the like.

A processor may include one or more cores that may enhance speed andperformance of a multiprocessor. In embodiments, the process may be adual core processor, quad core processors, other chip-levelmultiprocessor and the like that combine two or more independent cores(called a die).

The methods and systems described herein may be deployed in part or inwhole through a machine that executes computer software on a server,client, firewall, gateway, hub, router, or other such computer and/ornetworking hardware. The software program may be associated with aserver that may include a file server, print server, domain server,internet server, intranet server and other variants such as secondaryserver, host server, distributed server and the like. The server mayinclude one or more of memories, processors, computer readable media,storage media, ports (physical and virtual), communication devices, andinterfaces capable of accessing other servers, clients, machines, anddevices through a wired or a wireless medium, and the like. The methods,programs or codes as described herein and elsewhere may be executed bythe server. In addition, other devices required for execution of methodsas described in this application may be considered as a part of theinfrastructure associated with the server.

The server may provide an interface to other devices including, withoutlimitation, clients, other servers, printers, database servers, printservers, file servers, communication servers, distributed servers andthe like. Additionally, this coupling and/or connection may facilitateremote execution of program across the network. The networking of someor all of these devices may facilitate parallel processing of a programor method at one or more location without deviating from the scope ofthe invention. In addition, any of the devices attached to the serverthrough an interface may include at least one storage medium capable ofstoring methods, programs, code and/or instructions. A centralrepository may provide program instructions to be executed on differentdevices. In this implementation, the remote repository may act as astorage medium for program code, instructions, and programs.

The software program may be associated with a client that may include afile client, print client, domain client, internet client, intranetclient and other variants such as secondary client, host client,distributed client and the like. The client may include one or more ofmemories, processors, computer readable media, storage media, ports(physical and virtual), communication devices, and interfaces capable ofaccessing other clients, servers, machines, and devices through a wiredor a wireless medium, and the like. The methods, programs or codes asdescribed herein and elsewhere may be executed by the client. Inaddition, other devices required for execution of methods as describedin this application may be considered as a part of the infrastructureassociated with the client.

The client may provide an interface to other devices including, withoutlimitation, servers, other clients, printers, database servers, printservers, file servers, communication servers, distributed servers andthe like. Additionally, this coupling and/or connection may facilitateremote execution of program across the network. The networking of someor all of these devices may facilitate parallel processing of a programor method at one or more location without deviating from the scope ofthe invention. In addition, any of the devices attached to the clientthrough an interface may include at least one storage medium capable ofstoring methods, programs, applications, code and/or instructions. Acentral repository may provide program instructions to be executed ondifferent devices. In this implementation, the remote repository may actas a storage medium for program code, instructions, and programs.

The methods and systems described herein may be deployed in part or inwhole through network infrastructures. The network infrastructure mayinclude elements such as computing devices, servers, routers, hubs,firewalls, clients, personal computers, communication devices, routingdevices and other active and passive devices, modules and/or componentsas known in the art. The computing and/or non-computing device(s)associated with the network infrastructure may include, apart from othercomponents, a storage medium such as flash memory, buffer, stack, RAM,ROM and the like. The processes, methods, program codes, instructionsdescribed herein and elsewhere may be executed by one or more of thenetwork infrastructural elements.

The methods, program codes, and instructions described herein andelsewhere may be implemented on a cellular network having multiplecells. The cellular network may either be frequency division multipleaccess (FDMA) network or code division multiple access (CDMA) network.The cellular network may include mobile devices, cell sites, basestations, repeaters, antennas, towers, and the like. The cell networkmay be a GSM, GPRS, 3G, EVDO, mesh, or other networks types.

The methods, programs codes, and instructions described herein andelsewhere may be implemented on or through mobile devices. The mobiledevices may include navigation devices, cell phones, mobile phones,mobile personal digital assistants, laptops, palmtops, netbooks, pagers,electronic books readers, music players and the like. These devices mayinclude, apart from other components, a storage medium such as a flashmemory, buffer, RAM, ROM and one or more computing devices. Thecomputing devices associated with mobile devices may be enabled toexecute program codes, methods, and instructions stored thereon.Alternatively, the mobile devices may be configured to executeinstructions in collaboration with other devices. The mobile devices maycommunicate with base stations interfaced with servers and configured toexecute program codes. The mobile devices may communicate on a peer topeer network, mesh network, or other communications network. The programcode may be stored on the storage medium associated with the server andexecuted by a computing device embedded within the server. The basestation may include a computing device and a storage medium. The storagedevice may store program codes and instructions executed by thecomputing devices associated with the base station.

The computer software, program codes, and/or instructions may be storedand/or accessed on machine readable media that may include: computercomponents, devices, and recording media that retain digital data usedfor computing for some interval of time; semiconductor storage known asrandom access memory (RAM); mass storage typically for more permanentstorage, such as optical discs, forms of magnetic storage like harddisks, tapes, drums, cards and other types; processor registers, cachememory, volatile memory, non-volatile memory; optical storage such asCD, DVD; removable media such as flash memory (e.g. USB sticks or keys),floppy disks, magnetic tape, paper tape, punch cards, standalone RAMdisks, Zip drives, removable mass storage, off-line, and the like; othercomputer memory such as dynamic memory, static memory, read/writestorage, mutable storage, read only, random access, sequential access,location addressable, file addressable, content addressable, networkattached storage, storage area network, bar codes, magnetic ink, and thelike.

The methods and systems described herein may transform physical and/oror intangible items from one state to another. The methods and systemsdescribed herein may also transform data representing physical and/orintangible items from one state to another.

The elements described and depicted herein, including in flow charts andblock diagrams throughout the figures, imply logical boundaries betweenthe elements. However, according to software or hardware engineeringpractices, the depicted elements and the functions thereof may beimplemented on machines through computer executable media having aprocessor capable of executing program instructions stored thereon as amonolithic software structure, as standalone software modules, or asmodules that employ external routines, code, services, and so forth, orany combination of these, and all such implementations may be within thescope of the present disclosure. Examples of such machines may include,but may not be limited to, personal digital assistants, laptops,personal computers, mobile phones, other handheld computing devices,medical equipment, wired or wireless communication devices, transducers,chips, calculators, satellites, tablet PCs, electronic books, gadgets,electronic devices, devices having artificial intelligence, computingdevices, networking equipment, servers, routers and the like.Furthermore, the elements depicted in the flow chart and block diagramsor any other logical component may be implemented on a machine capableof executing program instructions. Thus, while the foregoing drawingsand descriptions set forth functional aspects of the disclosed systems,no particular arrangement of software for implementing these functionalaspects should be inferred from these descriptions unless explicitlystated or otherwise clear from the context. Similarly, it may beappreciated that the various steps identified and described above may bevaried, and that the order of steps may be adapted to particularapplications of the techniques disclosed herein. All such variations andmodifications are intended to fall within the scope of this disclosure.As such, the depiction and/or description of an order for various stepsshould not be understood to require a particular order of execution forthose steps, unless required by a particular application, or explicitlystated or otherwise clear from the context.

The methods and/or processes described above, and steps thereof, may berealized in hardware, software or any combination of hardware andsoftware suitable for a particular application. The hardware may includea general purpose computer and/or dedicated computing device or specificcomputing device or particular aspect or component of a specificcomputing device. The processes may be realized in one or moremicroprocessors, microcontrollers, embedded microcontrollers,programmable digital signal processors or other programmable device,along with internal and/or external memory. The processes may also, orinstead, be embodied in an application specific integrated circuit, aprogrammable gate array, programmable array logic, or any other deviceor combination of devices that may be configured to process electronicsignals. It may further be appreciated that one or more of the processesmay be realized as a computer executable code capable of being executedon a machine readable medium.

The computer executable code may be created using a structuredprogramming language such as C, an object oriented programming languagesuch as C++, or any other high-level or low-level programming language(including assembly languages, hardware description languages, anddatabase programming languages and technologies) that may be stored,compiled or interpreted to run on one of the above devices, as well asheterogeneous combinations of processors, processor architectures, orcombinations of different hardware and software, or any other machinecapable of executing program instructions.

Thus, in one aspect, each method described above and combinationsthereof may be embodied in computer executable code that, when executingon one or more computing devices, performs the steps thereof. In anotheraspect, the methods may be embodied in systems that perform the stepsthereof, and may be distributed across devices in a number of ways, orall of the functionality may be integrated into a dedicated, standalonedevice or other hardware. In another aspect, the means for performingthe steps associated with the processes described above may include anyof the hardware and/or software described above. All such permutationsand combinations are intended to fall within the scope of the presentdisclosure.

While the invention has been disclosed in connection with certainpreferred embodiments shown and described in detail, variousmodifications and improvements thereon may become readily apparent tothose skilled in the art. Accordingly, the spirit and scope of thepresent invention is not to be limited by the foregoing examples, but isto be understood in the broadest sense allowable by law.

All documents referenced herein are hereby incorporated by reference.

1. A method of content locality-based caching, comprising: processingdata that is associated with a data storage system with a processor todetermine its content locality; and caching a portion of the processeddata based on its determined content locality.
 2. The method of claim 1wherein the data that is associated with the data storage system ispre-cache data.
 3. The method of claim 1 wherein caching includescaching a first portion of the processed data in a Solid State Drive. 4.The method of claim 3 wherein the first portion of the processed datacomprises reference blocks.
 5. The method of claim 3 wherein the firstportion of the processed data comprises delta blocks.
 6. The method ofclaim 3 wherein the first portion of the processed data comprisesindependent blocks.
 7. The method of claim 1 wherein caching includescaching a first portion of the processed data in a Random Access Memory.8. The method of claim 7 wherein the first portion of the processed datacomprises delta blocks.
 9. The method of claim 7 wherein the firstportion of the processed data comprises independent blocks.
 10. Themethod of claim 1 wherein the caching includes caching a first portionof the processed data in a Hard Disk Drive (HDD).
 11. The method ofclaim 10 wherein the first portion of the processed data comprises deltablocks.
 12. The method of claim 10 wherein the first portion of theprocessed data comprises independent blocks.